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TAP CONTROLLER STATE DIAGRAM Figure 17-2
17.3 Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between
JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data
one stage towards the serial output at JTDO. A rising edge on JTCLK in the Exit1-IR state or the Exit2-
IR state with JTMS HIGH will move the controller to the Update-IR state The falling edge of that same
JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions
supported by the DS21354/554 with their respective operational binary codes are shown in Table 17-1.
INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE Table 17-1
Instruction
SAMPLE/PRELOAD
BYPASS
EXTEST
CLAMP
HIGHZ
IDCODE
Test Logic
1
Reset
0
1
Run Test/
0
Idle
0
Selected Register
Boundary Scan
Bypass
Boundary Scan
Bypass
Bypass
Device Identification
1
Select
DR-Scan
0
1
1
Capture DR
0
Shift DR
0
1
1
Exit DR
0
Pause DR
0
1
0
Exit2 DR
1
Update DR
1
0
81 of 117
DS21354 & DS21554
1
Select
IR-Scan
0
Capture IR
0
Shift IR
0
1
1
Exit IR
0
Pause IR
0
1
Exit2 IR
1
Update IR
1
0
Instruction Codes
010
111
000
011
100
001
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