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Dallas Semiconductor DS2154 Manual

Enhanced e1 single chip transceiver
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FEATURES
Complete E1(CEPT) PCM–30/ISDN–PRI transceiver
functionality
Onboard long and short haul line interface for clock/
data recovery and waveshaping
32–bit or 128–bit crystal–less jitter attenuator
Generates line build outs for both 120Ω and 75Ω lines
Frames to FAS, CAS, and CRC4 formats
Dual onboard two–frame elastic store slip buffers that
can connect to asynchronous backplanes up to
8.192 MHz
8–bit parallel control port that can be used directly on
either multiplexed or non–multiplexed buses
Extracts and inserts CAS signaling
Detects and generates Remote and AIS alarms
Programmable output clocks for Fractional E1, H0,
and H12 applications
Fully independent transmit and receive functionality
Full access to both Si and Sa bits aligned with CRC
multiframe
Four separate loopbacks for testing functions
Large counters for bipolar and code violations, CRC4
codeword errors, FAS errors, and E bits
Pin compatible with DS2152 T1 Enhanced Single–
Chip Transceiver
5V supply; low power CMOS
2
100–pin 14mm
body LQFP package
DESCRIPTION
The DS2154 Enhanced Single–Chip Transceiver
(ESCT) contains all of the necessary functions for con-
nection to E1 lines. The device is an upward compatible
version of the DS2153 Single–Chip Transceiver. The
onboard clock/data recovery circuitry coverts the AMI/
HDB3 E1 waveforms to a NRZ serial stream. The
DS2154 automatically adjusts to E1 22AWG (0.6 mm)
twisted–pair cables from 0 to over 2km in length. The
device can generate the necessary G.703 waveshapes
for both 75 ohm coax and 120 ohm twisted cables. The
onboard jitter attenuator (selectable to either 32 bits or
128 bits) can be placed in either the transmit or receive
Enhanced E1 Single Chip Transceiver
PACKAGE OUTLINE
1
ORDERING INFORMATION
DS2154L
(0 C to 70 C)
DS2154LN
(–40 C to +85 C)
data paths. The framer locates the frame and multi-
frame boundaries and monitors the data stream for
alarms. It is also used for extracting and inserting
signaling data, Si, and Sa bit information. The device
contains a set of internal registers which the user can
access to control the operation of the unit. Quick access
via the parallel control port allows a single controller to
handle many E1 lines. The device fully meets all of the
latest E1 specifications including ITU G.703, G.704,
G.706, G.823, G.932, and I.431 as well as ETS 300 011,
300 233, 300 166, TBR 12 and TBR 13.
DS2154
DS2154
071498 1/71

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  • Page 1 HDB3 E1 waveforms to a NRZ serial stream. The access to control the operation of the unit. Quick access DS2154 automatically adjusts to E1 22AWG (0.6 mm) via the parallel control port allows a single controller to twisted–pair cables from 0 to over 2km in length. The handle many E1 lines.

  • Page 2: Table Of Contents

    DS2154 TABLE OF CONTENTS I.0 INTRODUCTION ..............
  • Page 3 DS2154 12.0 LINE INTERFACE FUNCTIONS ............

  • Page 4: Introduction

    DS2154 1.0 INTRODUCTION features listed below. All of the original features of the The DS2154 is a super–set version of the popular DS2153 have been retained and software created for DS2153 E1 Single–Chip Transceiver offering the new the original devices is transferrable into the DS2154.
  • Page 5 DS2154 DS2154 ENHANCED E1 SINGLE–CHIP TRANSCEIVER Figure 1–1 PER–CHANNEL CODE INSERT PER–CHANNEL CODE INSERT SA AND SI EXTRACTION FAS WORD INSERTION SIGNALING EXTRACTION SI BIT INSERTION E–BIT COUNTER E–BIT INSERTION FAS ERROR COUNTER SA INSERTION CRC ERROR COUNTER PER–CHANNEL LOOPBACK...

  • Page 6: Pin List

    The DS2154 will drive the E1 serial stream is analyzed to locate the framing/multi- line from the TTIP and TRING pins via a coupling trans- frame pattern.
  • Page 7 DS2154 SYMBOL TYPE DESCRIPTION – No Connect. – No Connect. Bus Type Select. LIUC Line Interface Connect. 8XCLK Eight Times Clock. TEST Test. – No Connect. RTIP Receive Analog Tip Input. RRING Receive Analog Ring Input. RVDD – Receive Analog Positive Supply.
  • Page 8 DS2154 SYMBOL TYPE DESCRIPTION DVDD – Digital Positive Supply. DVSS – Digital Signal Ground. TCLK Transmit Clock. TSER Transmit Serial Data. TSIG Transmit Signaling Input. TESO Transmit Elastic Store Output. TDATA Transmit Data. TSYSCLK Transmit System Clock. TSSYNC Transmit System Sync.
  • Page 9 RSYSCLK Receive System Clock. NOTE: Leave all no connect (NC) pins open circuited. DS2154 PIN DESCRIPTION Table 1–2 TRANSMIT SIDE DIGITAL PINS Transmit Channel Clock [TCHCLK]. A 256 KHz clock Transmit Clock [TCLK]. A 2.048 MHz primary clock. which pulses high during the LSB of each channel. Syn- Used to clock data through the transmit side formatter.
  • Page 10 DS2154 enabled. Useful for blocking clocks to a serial UART or Transmit Data [TDATA]. Sampled on the falling edge of TCLK with data to be clocked through the transmit LAPD controller in applications where not all E1 chan- nels are used such as Fractional E1, 384 Kbps (H0), side formatter.
  • Page 11 768K bps, or ISDN–PRI. Also useful for locating individ- interface detects a loss of carrier. [Note: a test mode exists to allow the DS2154 to detect carrier loss at ual channels in drop–and–insert applications, for exter- RPOSI and RNEGI in place of detection at RTIP and nal per–channel loopback, and for per–channel condi-...
  • Page 12 DS2154 Receive Clock Input [RCLKI]. Clock used to clock Write Input [WR] (Read/Write [R/W]). WR is an active data through the receive side framer. This pin is nor- low signal. mally tied to RCLKO. Can be internally connected to RCLKO by tying the LIUC pin high.
  • Page 13 5%. Should be tied to the RVDD and DVDD pins. be tied to the RVSS and DVSS pins. Digital Signal Ground [DVSS]. 0.0 volts. Should be tied to the RVSS and TVSS pins. DS2154 REGISTER MAP Table 1–3 ADDRESS REGISTER NAME REGISTER ABBREVIATION BPV or Code Violation Count 1.
  • Page 14 DS2154 ADDRESS REGISTER NAME REGISTER ABBREVIATION Common Control 2. CCR2 Common Control 3. CCR3 Transmit Sa Bit Control. TSaCR – Not present. – Synchronizer Status. Receive Non–Align Frame. RNAF Transmit Align Frame. Transmit Non–Align Frame. TNAF Transmit Channel Blocking 1.
  • Page 15 DS2154 ADDRESS REGISTER NAME REGISTER ABBREVIATION Receive Signaling 12. RS12 Receive Signaling 13. RS13 Receive Signaling 14. RS14 Receive Signaling 15. RS15 Receive Signaling 16. RS16 Transmit Signaling 1. Transmit Signaling 2. Transmit Signaling 3. Transmit Signaling 4. Transmit Signaling 5.
  • Page 16 DS2154 ADDRESS REGISTER NAME REGISTER ABBREVIATION Receive Sa5 Bits. RSa5 Receive Sa6 Bits. RSa6 Receive Sa7 Bits. RSa7 Receive Sa8 Bits. RSa8 Transmit Channel 1. Transmit Channel 2. Transmit Channel 3. Transmit Channel 4. Transmit Channel 5. Transmit Channel 6.
  • Page 17 DS2154 ADDRESS REGISTER NAME REGISTER ABBREVIATION Transmit Channel 30. TC30 Transmit Channel 31. TC31 Transmit Channel 32. TC32 Receive Channel 1. Receive Channel 2. Receive Channel 3. Receive Channel 4. Receive Channel 5. Receive Channel 6. Receive Channel 7. Receive Channel 8.

  • Page 18: Parallel Port

    Section 14 for more details. the MSB to determine which chip is present since in the DS2154 the MSB will be set to a one and in the DS2152 3.0 CONTROL, ID AND TEST REGISTERS it will be set to a zero. The lower four bits of the IDR are The operation of the DS2154 is configured via a set of used to display the die revision of the chip.
  • Page 19 DS2154 IDR: DEVICE IDENTIFICATION REGISTER (Address= 0F Hex) (MSB) (LSB) T1E1 SYMBOL POSITION NAME AND DESCRIPTION T1E1 IDR.7 T1 or E1 Chip Determination Bit. 0=T1 chip 1=E1 chip IDR.3 Chip Revision Bit 3. MSB of a decimal code that represents the chip revi- sion.
  • Page 20 DS2154 SYNC/RESYNC CRITERIA Table 3–1 FRAME OR MULTI- FRAME LEVEL SYNC CRITERIA RESYNC CRITERIA ITU SPEC. FAS present in frame N and Three consecutive incorrect G.706 N + 2, and FAS not present in FAS received 4.1.1 frame N + 1 4.1.2...
  • Page 21 1=CAS and CRC4 multiframe mode (see the timing in Section 13) TSIO TCR1.0 TSYNC I/O Select. 0=TSYNC is an input 1=TSYNC is an output NOTE: See Figure 13–11 for more details about how the Transmit Control Registers affect the operation of the DS2154. 071498 21/71...
  • Page 22 DS2154 TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex) (MSB) (LSB) Sa8S Sa7S Sa6S Sa5S Sa4S AEBE SYMBOL POSITION NAME AND DESCRIPTION Sa8S TCR2.7 Sa8 Bit Select. Set to one to source the Sa8 bit from the TLINK pin; set to zero to not source the Sa8 bit.

  • Page 23: Framers Loopback

    1=CRC4 enabled FRAMER LOOPBACK 1. Data will be transmitted as normal at TPOSO and When CCR1.7 is set to a one, the DS2154 will enter a TNEGO. Framer LoopBack (FLB) mode. See Figure 1–1 for 2. Data input via RPOSI and RNEGI will be ignored.

  • Page 24: Automatic Alarm Generation

    When either CCR2.4 or CCR2.5 is set to one, the and TNEGO pins. It is an illegal state to have both DS2154 monitors the receive side to determine if any of CCR2.4 and CCR2.5 set to one at the same time. If the following conditions are present: loss of receive CCR2.4=1, then RAI will be transmitted according to...

  • Page 25: Power-Up Sequence

    CCR4.0 Transmit Channel Monitor Bit 0. LSB of the channel decode. REMOTE LOOPBACK When CCR4.7 is set to a one, the DS2154 will be forced LOCAL LOOPBACK into Remote LoopBack (RLB). In this loopback, data When CCR4.6 is set to a one, the DS2154 will be forced input via the RPOSI and RNEGI pins will be transmitted into Local LoopBack (LLB).

  • Page 26: Status And Information Registers

    There is a set of four registers that contain information ter. The read result should be logically AND’ed with the on the current real time status of the DS2154, Status mask byte that was just written and this value should be...
  • Page 27 DS2154 RDMA, RSA0, RSLIP, RMF, RAF, TMF, SEC, TAF, occur If the alarm is still present, the register bit will re- LOTC, RCMF, and TSLIP. The four interrupts will force main set. the INT pin low whenever the alarm changes state (i.e.,...

  • Page 28: Crc4 Sync Counter

    Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0=1) consecutive zeros have been detected at RTIP and RRING. [Note: a test mode exists to allow the DS2154 to detect carrier loss at RPOSI and RNEGI in place of detection at RTIP and RRING].
  • Page 29 DS2154 ALARM CRITERIA Table 4–1 ALARM SET CRITERIA CLEAR CRITERIA SPEC. RSA1 over 16 consecutive frames (one full over 16 consecutive frames (one full G.732 (receive signaling MF) timeslot 16 contains less than MF) timeslot 16 contains three or all ones)
  • Page 30 DS2154 IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex) (MSB) (LSB) RSA1 RDMA RSA0 RSLIP RUA1 RLOS SYMBOL POSITION NAME AND DESCRIPTION RSA1 IMR1.7 Receive Signaling All Ones / Signaling Change. 0=interrupt masked 1=interrupt enabled RDMA IMR1.6 Receive Distant MF Alarm.

  • Page 31: Error Count Registers

    5.0 ERROR COUNT REGISTERS 16–bit counter that records either BiPolar Violations There are a set of four counters in the DS2154 that (BPVs) or Code Violations (CVs). If CCR2.6=0, then the record bipolar or code violations, errors in the CRC4 VCR counts bipolar violations.

  • Page 32: Crc4 Error Counter

    DS2154 5.2 CRC4 Error Counter CRC4 count in a one second period is 1000, this counter CRC4 Count Register 1 (CRCCR1) is the most signifi- cannot saturate. The counter is disabled during loss of cant word and CRCCR2 is the least significant word of a sync at either the FAS or CRC4 level;...

  • Page 33: Fas Error Counter

    6.0 DS0 MONITORING FUNCTION The TCM4 to TCM0 and RCM4 to RCM0 bits should be The DS2154 has the ability to monitor one DS0 64 Kbps programmed with the decimal decode of the appropriate channel in the transmit direction and one DS0 channel E1 channel.
  • Page 34 DS2154 TCM2 CCR4.2 Transmit Channel Monitor Bit 2. TCM1 CCR4.1 Transmit Channel Monitor Bit 1. TCM0 CCR4.0 Transmit Channel Monitor Bit 0. LSB of the channel decode that deter- mines which transmit DS0 channel data will appear in the TDS0M register.

  • Page 35: Signaling Operation

    7.0 SIGNALING OPERATION The DS2154 contains provisions for both processor the DS2154. Each of the 30 voice channels has four based (i.e., software based) signaling bit access and for signaling bits (A/B/C/D) associated with it. The num- hardware based access. Both the processor based...
  • Page 36 DS2154 RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address=30 to 3F Hex) (MSB) (LSB) RS1 (30) A(1) B(1) C(1) D(1) A(16) B(16) C(16) D(16) RS2 (31) A(2) B(2) C(2) D(2) A(17) B(17) C(17) D(17) RS3 (32) A(3) B(3) C(3) D(3) A(18)
  • Page 37 TCR1.5. alarm is to be transmitted, then the TS1.2 bit should be On multiframe boundaries, the DS2154 will load the val- cleared. The three remaining bits in TS1 are the spare ues present in the Transmit Signaling Register into an bits.

  • Page 38: Hardware Based Signaling

    Transmit Side each channel. See the timing diagrams in Section 13 for Via the THSE control bit (CCR3.2), the DS2154 can be an example. The RSIG data is updated once a multi- set up to take the signaling data presented at the TSIG frame (2 ms) unless a freeze is in effect.

  • Page 39: Per-Channel Code Generation

    E1 line. with data generated by the DS2154. The first method See Figure 1–1. If this mode is enabled, then transmit which is covered in Section 8.1.1 was a feature con-...
  • Page 40 DS2154 TIR1/TIR2/TIR3/TIR4: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex) [Also used for Per–Channel Loopback] (MSB) (LSB) TIR1 (26) CH16 CH15 CH14 CH13 CH12 CH11 CH10 TIR2 (27) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TIR3 (28) CH32 CH31 CH30...

  • Page 41: Receive Side Code Generation

    DS2154 TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER (Address=A0 to A3 Hex) (MSB) (LSB) TCC1 (A0) CH16 CH15 CH14 CH13 CH12 CH11 CH10 TCC2 (A1) CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TCC3 (A2) CH32 CH31 CH30 CH29 CH28 CH27 CH26...

  • Page 42: Clock Blocking Registers

    DS2154 9.0 CLOCK BLOCKING REGISTERS the RCHBLK and TCHBLK pin will be held high during the entire corresponding channel time. See the timing in The Receive Channel blocking Registers (RCBR1 / Section 13 for an example. The TCBRs have alternate RCBR2 / RCBR3 / RCBR4) and the Transmit Channel mode of use.

  • Page 43: Elastic Stores Operation

    *=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm bits. 10.0 ELASTIC STORES OPERATION set to one. The DS2154 will always indicate frame The DS2154 contains dual two–frame (512 bits) elastic boundaries via the RFSYNC output whether the elastic stores, one for the receive direction, and one for the store is enabled or not.

  • Page 44: Additional (Sa) And International (Si) Bit Operation

    INTERNATIONAL (Si) BIT OPERATION ing of the TCR1.3 bit. Please see the timing diagrams The DS2154 provides for access to both the Sa and the and the transmit data flow diagram in Section 13 for Si bits via three different methods. The first is via a hard- examples.
  • Page 45 Additional Bit 7. RNAF.0 Additional Bit 8. TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex) (MSB) (LSB) [Must be programmed with the seven bit FAS word; the DS2154 does not automatically set these bits] SYMBOL POSITION NAME AND DESCRIPTION TAF.7 International Bit.

  • Page 46: Internal Register Scheme Based On Crc4 Multiframe

    DS2154 TNAF.5 Remote Alarm (used to transmit the alarm). TNAF.4 Additional Bit 4. TNAF.3 Additional Bit 5. TNAF.2 Additional Bit 6. TNAF.1 Additional Bit 7. TNAF.0 Additional Bit 8. 11.3 INTERNAL REGISTER SCHEME On the transmit side, there is also a set of eight registers...
  • Page 47 DS2154 REGISTER ADDRESS NAME (HEX) FUNCTION RSiAF The eight Si bits in the align frame RSiNAF The eight Si bits in the non–align frame The eight reportings of the receive remote alarm (RA) RSa4 The eight Sa4 reported in each CRC4 multiframe...
  • Page 48 1=insert data from the TSa8 register into the transmit data stream 12.0 LINE INTERFACE FUNCTIONS The line interface function in the DS2154 contains three drives the E1 line, and (3) the jitter attenuator. Each of sections; (1) the receiver which handles clock and data...
  • Page 49 27 ohms NOTE: 1. This LBO is not recommended for use in the A2 revision of the DS2154. Due to the nature of the design of the transmitter in the transformer as shown in Figure 12–1. In order for the DS2154, very little jitter (less then 0.005 UIpp broad-...
  • Page 50 DS2154 12.3 JITTER ATTENUATOR The DS2154 contains an onboard jitter attenuator that capacitors should be placed from each leg of the crystal can be set to a depth of either 32 or 128 bits via the to ground as shown in Figure 12–1. Onboard circuitry JABDS bit in the Line Interface Control Register (LICR).
  • Page 51 É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É É 2.4K 100K FREQUENCY (Hz) DS2154 TRANSMIT WAVEFORM TEMPLATE Figure 12–3 1. 2 1. 1 269 ns 1. 0 0.
  • Page 52 DS2154 DS2154 JITTER ATTENUATION Figure 12–4 0 dB Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê ITU G.7XX PROHIBITED AREA Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê Ê...
  • Page 53 DS2154 13.0 TIMING DIAGRAMS/SYNC FLOWCHART/TRANSMIT DATA FLOW DIAGRAM RECEIVE SIDE TIMING Figure 13–1 FRAME# 13 14 RSYNC RFSYNC RSYNC RLCLK RLINK NOTES: 1. RSYNC in the frame mode (RCR1.6=0). 2. RSYNC in the multiframe mode (RCR1.6=1). 3. RLCLK is programmed to pulse high during the Sa4 bit position.
  • Page 54 DS2154 RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (WITH ELASTIC STORE ENABLED) Figure 13–3 RSYSCLK CHANNEL 23/31 CHANNEL 24/32 CHANNEL 1/2 RSER RSYNC RMSYNC RSYNC RCHCLK RCHBLK NOTES: 1. Data from the E1 Channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (Channel 2 from the E1 link is mapped to Channel 1 of the T1 link, etc.) and the F–bit position is added (forced to one).
  • Page 55 DS2154 TRANSMIT SIDE TIMING Figure 13–5 FRAME# TSYNC TFSYNC TSYNC TLCLK TLINK NOTES: 1. TSYNC in the frame mode (TCR1.1=0). 2. TSYNC in the multiframe mode (TCR1.1=1). 3. TLINK is programmed to source only the Sa4 bit. 4. This diagram assumes both the CAS MF and the CRC4 begin with the align frame.
  • Page 56 F–BIT TSSYNC TCHCLK TCHBLK NOTES: 1. TCHBLK is programmed to block Channel 23. 2. The F–bit position is ignored by the DS2154. TRANSMIT SIDE 2.048 MHz (WITH ELASTIC STORE ENABLED) Figure 13–8 TSYSCLK CHANNEL 31 CHANNEL 32 CHANNEL 1 TSER...
  • Page 57 DS2154 G.802 TIMING Figure 13–9 TIMESLOT# 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3...
  • Page 58 DS2154 DS2154 SYNCHRONIZATION FLOWCHART Figure 13–10 POWER UP RLOS=1 FAS SEARCH FASSA=1 RLOS=1 FAS SYNC CRITERIA MET FASSA=0 RESYNC IF RCR1.1=0 CRC4 MULTIFRAME CAS MULTIFRAME INCREMENT CRC4 8 MS SEARCH (IF ENABLED SEARCH (IF ENABLED SYNC COUNTER; TIME VIA CCR 1.0) VIA CCR1.3)
  • Page 59 DS2154 DS2154 TRANSMIT DATA FLOW Figure 13–11 TSER & TSIG TDATA TCBR1 TO TCBR4 HARDWARE SIGNALING CCR3.5 INSERTION CCR3.2 TC1 TO TC32 RSER PER–CHANNEL CODE TLINK (note 1) GENERATION (TCC1/2/3/4) TNAF TIMESLOT 0 PASS–THROUGH (TCR1.6) Si BIT INSERTION RECEIVE SIDE...
  • Page 60 DS2154 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground –1.0V to +7.0V Operating Temperature for DS2154L 0 C to 70 C Operating Temperature for DS2154LN –40 C to +85 C Storage Temperature –55 C to +125 C Soldering Temperature...
  • Page 61 DS2154 AC CHARACTERISTICS – MULTIPLEXED PARALLEL PORT (MUX=1) (0 C to 70 C; V 5% for DS2154L; –40 C to + C; V 5% for DS2154LN) PARAMETER SYMBOL UNITS NOTES Cycle Time Pulse Width, DS low or RD high Pulse Width, DS high or RD low...
  • Page 62 DS2154 AC CHARACTERISTICS – RECEIVE SIDE (0 C to 70 C; V 5% for DS2154L; –40 C to + C; V 5% for DS2154LN) PARAMETER SYMBOL UNITS NOTES RCLKO Period RCLKO Pulse Width RCLKO Pulse Width RCLKI Period RCLKI Pulse Width...
  • Page 63 DS2154 14.0 A. C. AND D. C. CHARACTERISTICS INTEL BUS READ AC TIMING (BTS=0/MUX=1) Figure 14–1 ASED AD0-AD7 INTEL BUS WRITE AC TIMING (BTS=0/MUX=1) Figure 14–2 ASED AD0-AD7 071498 63/71...
  • Page 64 DS2154 MOTOROLA BUS AC TIMING (BTS=1/MUX=1) Figure 14–3 ASED AD0-AD7 (READ) AD0-AD7 (WRITE) RECEIVE SIDE AC TIMING Figure 14–4 RCLK MSB OF RSER/RDATA/RSIG CHANNEL 1 RCHCLK RCHBLK RFSYNC/RMSYNC RSYNC RLCLK Sa4 TO Sa8 RLINK BIT POSITION NOTES: 1. RSYNC is in the output mode (RCR1.5=0).
  • Page 65 DS2154 AC CHARACTERISTICS – TRANSMIT SIDE (0 C to 70 C; V 5% for DS2154L; –40 C to + C; V 5% for DS2154LN) PARAMETER SYMBOL UNITS NOTES TCLK Period TCLK Pulse Width TCLKI Period TCLKI Pulse Width TSYSCLK Period...
  • Page 66 DS2154 RECEIVE SYSTEM SIDE AC TIMING Figure 14–5 RSYSCLK RSER/RSIG OF CHANNEL 1 RCHCLK RCHBLK RMSYNC RSYNC RSYNC NOTES: 1. RSYNC is in the output mode (RCR1.5=0). 2. RSYNC is in the input mode (RCR1.5=1). RECEIVE LINE INTERFACE AC TIMING Figure 14–6...
  • Page 67 DS2154 TRANSMIT SIDE AC TIMING Figure 14–7 TCLK TESO TSER/TSIG/ TDATA TCHCLK TCHBLK TSYNC TSYNC TLCLK TLINK NOTES: 1. TSYNC is in the output mode (TCR1.0=1). 2. TSYNC is in the input mode (TCR1.0=0). 3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
  • Page 68 DS2154 TRANSMIT SYSTEM SIDE AC TIMING Figure 14–8 TSYSCLK TSER TCHCLK TCHBLK TSSYNC NOTES: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
  • Page 69 DS2154 AC CHARACTERISTICS – NON–MULTIPLEXED PARALLEL PORT (MUX=0 ) (0 C to 70 C; V 5% for DS2154T; –40 C to + C; V 5% for DS2154TN) PARAMETER SYMBOL UNITS NOTES Set Up Time for A0 to A7 Valid to...
  • Page 70 DS2154 INTEL BUS WRITE AC TIMING (BTS=0/MUX=0) Figure 14–11 10 ns min. A0 TO A7 ADDRESS VALID D0 TO D7 10 ns 0 ns min. min. 0 ns min. 0 ns min. 0 ns min. 75 ns min. MOTOROLA BUS READ AC TIMING (BTS=1/MUX=0) Figure 14–12...
  • Page 71 DS2154 DS2154 100–PIN LQFP 100–PIN – 1.60 0.05 – 1.35 1.45 0.17 0.27 0.09 0.20 15.80 16.20 14.00 BSC 15.80 16.20 14.00 BSC 0.50 BSC 0.45 0.75 071498 71/71...

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