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SYMBOL
POSITION NAME AND DESCRIPTION
TDS0M
TDC1.5
TD4
TDC1.4
TD3
TDC1.3
TD2
TDC1.2
TD1
TDC1.1
TD0
TDC1.0
TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address=BB Hex)
(MSB)
TDB8
TDB7
SYMBOL
POSITION NAME AND DESCRIPTION
TDB8
TDC2.7
TDB7
TDC2.6
TDB6
TDC2.5
TDB5
TDC2.4
TDB4
TDC2.3
TDB3
TDC2.2
TDB2
TDC2.1
TDB1
TDC2.0
16 LINE INTERFACE FUNCTIONS
The line interface function in the DS21354/554 contains three sections; (1) the receiver which handles
clock and data recovery, (2) the transmitter which waveshapes and drives the E1 line, and (3) the jitter
attenuator. Each of the these three sections is controlled by the Line Interface Control Register (LICR)
which is described below.
LICR: LINE INTERFACE CONTROL REGISTER (Address=18 Hex)
(MSB)
L2
L1
SYMBOL
POSITION NAME AND DESCRIPTION
L2
LICR.7
L1
LICR.6
L0
LICR.5
EGL
LICR.4
DS0 Selection Mode.
0 = utilize the TD0 to TD4 bits to select which single DS0 channel to use.
1 = utilize the TCHBLK control registers to select which DS0 channels to
use.
DS0 Channel Select Bit 4. MSB of the DS0 channel select.
DS0 Channel Select Bit 3.
DS0 Channel Select Bit 2.
DS0 Channel Select Bit 1.
DS0 Channel Select Bit 0. LSB of the DS0 channel select.
TDB6
TDB5
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit
from being used.
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used.
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used.
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from being used.
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from being used.
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from being used.
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from being used.
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to stop this bit
from being used.
L0
EGL
Line Build Out Select Bit 2. Sets the transmitter build out; see Table 16-
1 and Table 16-2.
Line Build Out Select Bit 1. Sets the transmitter build out; see Table 16-
1 and Table 16-2.
Line Build Out Select Bit 0. Sets the transmitter build out; see Table 16-
1 and Table 16-2.
Receive Equalizer Gain Limit.
0 = –12 dB
1 = –43 dB
68 of 117
TDB4
TDB3
JAS
JABDS
DS21354 & DS21554
(LSB)
TDB2
TDB1
(LSB)
DJA
TPD
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