Hdlc Register Description - Dallas Semiconductor DS21354L Manual

15.4 HDLC Register Description

HCR: HDLC CONTROL REGISTER (Address=B0 Hex)
(MSB)
– RHR
SYMBOL POSITION NAME AND DESCRIPTION
– HCR.7
RHR HCR.6
TFS HCR.5
THR HCR.4
TABT HCR.3
TEOM HCR.2
TZSD HCR.1
TCRCD HCR.0
HSR: HDLC STATUS REGISTER (Address=B1 Hex)
(MSB)
FRCL RPE
SYMBOL POSITION NAME AND DESCRIPTION
FRCL HSR.7
RPE HSR.6
RPS HSR.5
TFS THR
Not Assigned. Should be set to zero when written.
Receive HDLC Reset. A 0 to 1 transition will reset the HDLC controller.
Must be cleared and set again for a subsequent reset.
Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
Transmit HDLC Reset. A 0 to 1 transition will reset the HDLC
controller. Must be cleared and set again for a subsequent reset.
Transmit Abort. A 0 to 1 transition will cause the FIFO contents to be
dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle
until a new packet is initiated by writing new data into the FIFO. Must be
cleared and set again for a subsequent abort to be sent.
Transmit End of Message. Should be set to a one just before the last data
byte of a HDLC packet is written into the transmit FIFO at THFR. This bit
will be cleared by the HDLC controller when the last byte has been
transmitted.
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
RPS RHALF
Framer Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0 = 1)
consecutive zeros have been detected at RPOSI and RNEGI.
Receive Packet End. Set when the HDLC controller detects either the
finish of a valid message (i.e., CRC check complete) or when the
controller has experienced a message fault such as a CRC checking error,
or an overrun condition, or an abort has been seen. The setting of this bit
prompts the user to read the RHIR register for details.
Receive Packet Start. Set when the HDLC controller detects an opening
byte. The setting of this bit prompts the user to read the RHIR register for
details.
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TABT TEOM
RNE THALF
DS21354 & DS21554
(LSB)
TZSD TCRCD
(LSB)
TNF TMEND