Dallas Semiconductor MAXIM DS21354 Manuals

Manuals and User Guides for Dallas Semiconductor MAXIM DS21354. We have 1 Dallas Semiconductor MAXIM DS21354 manual available for free PDF download: Manual

Dallas Semiconductor MAXIM DS21354 Manual (124 pages)

3.3V/5V E1 Single-Chip Transceivers

Brand: Dallas Semiconductor | Category: Transceiver | Size: 0 MB

Table of Contents
2
Introduction
6
Functional Description
7
Document Revision History
8
Block Diagram
9
Figure 2-1. DS21354/554 Block Diagram
9
Pin Description
10
Table 3-1. Pin Description Sorted by Pin Number
10
Table 3-2. Pin Description by Symbol
12
Pin Function Description
14
Transmit-Side Pins
14
Receive-Side Pins
17
Parallel Control Port Pins
20
JTAG Test Access Port Pins
22
Interleave Bus Operation Pins
22
Line Interface Pins
23
Supply Pins
24
Parallel Port
25
Register Map
25
Table 4-1. Register Map Sorted by Address
25
Control, ID, and Test Registers
30
Power-Up Sequence
30
Table 5-1. Device ID Bit Map
30
Synchronization and Resynchronization
32
Table 5-2. SYNC/RESYNC Criteria
32
Framer Loopback
36
Automatic Alarm Generation
38
Remote Loopback
40
Local Loopback
40
Status and Information Registers
43
Crc4 Sync Counter
45
Table 6-1. Alarm Criteria
46
Error Count Registers
50
Bpv or Code Violation Counter
50
Crc4 Error Counter
51
E-Bit Counter
51
Fas Error Counter
52
Ds0 Monitoring Function
53
Signaling Operation
56
Processor-Based Signaling
56
Hardware-Based Signaling
58
Receive Side
58
Transmit Side
59
Per-Channel Code Generation and Loopback
60
Transmit-Side Code Generation
60
Simple Idle Code Insertion and Per-Channel Loopback
60
Per-Channel Code Insertion
61
Receive-Side Code Generation
62
Clock Blocking Registers
63
Elastic Stores Operation
65
Receive Side
65
Transmit Side
65
Additional (Sa) and International (Si) Bit Operation
66
Hardware Scheme
66
Internal Register Scheme Based on Double Frame
66
Internal Register Scheme Based on Crc4 Multiframe
68
Hdlc Controller for the Sa Bits or Ds0
70
General Overview
70
Table 14-1. HDLC Controller Register List
70
Hdlc Status Registers
71
Basic Operation Details
72
Example: Receive an HDLC Message
72
Example: Transmit an HDLC Message
72
Hdlc Register Description
73
Line Interface Functions
80
Receive Clock and Data Recovery
81
Transmit Waveshaping and Line Driving
81
Table 15-1. Line Build-Out Select in LICR for the DS21554
81
Jitter Attenuator
82
Table 15-2. Line Build-Out Select in LICR for the DS21354
82
Table 15-3. Transformer Specifications
82
Figure 15-1. Basic External Analog Connections
83
Figure 15-2. Optional Crystal Connection
83
Figure 15-3. Jitter Tolerance
84
Figure 15-4. Jitter Attenuation
84
Figure 15-5. Transmit Waveform Template
85
Protected Interfaces
86
Figure 15-6. Protected Interface Example for the DS21554
87
Figure 15-7. Protected Interface Example for the DS21354
88
Receive Monitor Mode
89
Figure 15-8. Typical Monitor Port Application
89
Table 15-4. Receive Monitor Mode Gain
89
Jtag Boundary Scan Architecture and Test Access Port
90
Figure 16-1. JTAG Functional Block Diagram
91
Figure 16-2. TAP Controller State Diagram
94
Instruction Register
95
Table 16-1. Instruction Codes for IEEE 1149.1 Architecture
95
Test Registers
96
Table 16-2. ID Code Structure
96
Table 16-3. Device ID Codes
96
Table 16-4. Boundary Scan Control Bits
97
Interleaved Pcm Bus Operation
98
Table 17-1. IBO Master Device Select
98
Channel Interleave
99
Frame Interleave
99
Figure 17-1. IBO Basic Configuration Using Four Scts
99
Functional Timing Diagrams
100
Receive
100
Figure 18-1. Receive-Side Timing
100
Figure 18-2. Receive-Side Boundary Timing (with Elastic Store Disabled)
100
Figure 18-3. Receive-Side 1.544Mhz Boundary Timing (with Elastic Store Enabled)
101
Figure 18-4. Receive-Side 2.048Mhz Boundary Timing (with Elastic Store Enabled)
101
Figure 18-5. Receive-Side Interleave Bus Operation, Byte Mode
102
Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode
103
Transmit
104
Figure 18-7. Transmit-Side Timing
104
Figure 18-8. Transmit-Side Boundary Timing (with Elastic Store Disabled)
104
Figure 18-9. Transmit-Side 1.544Mhz Boundary Timing (with Elastic Store Enabled)
105
Figure 18-10. Transmit-Side 2.048Mhz Boundary Timing (with Elastic Store Enabled)
105
Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode
106
Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode
107
Figure 18-13. G.802 Timing
108
Figure 18-14. DS21354/DS21554 Framer Synchronization Flowchart
109
Figure 18-15. DS21354/DS21554 Transmit Data Flow
110
Operating Parameters
111
Ac Timing Parameters and Diagrams
112
Multiplexed Bus Ac Characteristics
112
Figure 20-1. Intel Bus Read Ac Timing (BTS = 0/MUX = 1)
113
Figure 20-2. Intel Bus Write Timing (BTS = 0/MUX = 1)
113
Figure 20-3. Motorola Bus AC Timing (BTS = 1/MUX = 1)
114
Nonmultiplexed Bus Ac Characteristics
115
Figure 20-4. Intel Bus Read AC Timing (BTS = 0/MUX = 0)
115
Figure 20-5. Intel Bus Write AC Timing (BTS = 0/MUX = 0)
116
Figure 20-6. Motorola Bus Read AC Timing (BTS = 1/MUX = 0)
116
Figure 20-7. Motorola Bus Write AC Timing (BTS = 1/MUX = 0)
116
Receive-Side AC Characteristics
117
Figure 20-8. Receive-Side AC Timing
118
Figure 20-9. Receive System Side AC Timing
119
Figure 20-10. Receive Line Interface AC Timing
120
Transmit Ac Characteristics
121
Figure 20-11. Transmit-Side AC Timing
122
Figure 20-12. Transmit System Side AC Timing
123
Figure 20-13. Transmit Line Interface Side AC Timing
123
Package Information
124

Dallas Semiconductor Categories

Transceiver Multiplexer Motherboard Industrial Electrical

More Dallas Semiconductor Manuals

Dallas Semiconductor MAXIM DS21354 Manuals

Dallas Semiconductor MAXIM DS21354 Manual (124 pages)

Table of Contents

Related Products

Dallas Semiconductor Categories