Error Count Registers; Bpv Or Code Violation Counter - Dallas Semiconductor DS21354L Manual

E1 single chip transceivers;
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IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)
(MSB)
RMF
RAF
SYMBOL
POSITION NAME AND DESCRIPTION
RMF
IMR2.7
RAF
IMR2.6
TMF
IMR2.5
SEC
IMR2.4
TAF
IMR2.3
LOTC
IMR2.2
RCMF
IMR2.1
TSLIP
IMR2.0

8 ERROR COUNT REGISTERS

There are a set of four counters in the DS21354/554 that record bipolar or code violations, errors in the
CRC4 SMF code words, E bits as reported by the far end, and word errors in the FAS. Each of these four
counters are automatically updated on either one second boundaries (CCR2.7 = 0) or every 62.5 ms
(CCR2.7 = 1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain
performance data from either the previous second or the previous 62.5 ms. The user can use the interrupt
from the one second timer to determine when to read these registers. The user has a full second (or 62.5
ms) to read the counters before the data is lost. All four counters will saturate at their respective
maximum counts and they will not rollover.

8.1 BPV or Code Violation Counter

Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of
a 16–bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6 = 0,
then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same
polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 code words
are not counted as BPVs. If CCR2.6 = 1, then the VCR counts code violations as defined in ITU O.161.
Code violations are defined as consecutive bipolar violations of the same polarity.
TMF
SEC
Receive CAS Multiframe.
0 = interrupt masked
1 = interrupt enabled
Receive Align Frame.
0 = interrupt masked
1 = interrupt enabled
Transmit Multiframe.
0 = interrupt masked
1 = interrupt enabled
One Second Timer.
0 = interrupt masked
1 = interrupt enabled
Transmit Align Frame.
0 = interrupt masked
1 = interrupt enabled
Loss Of Transmit Clock.
0 = interrupt masked
1 = interrupt enabled
Receive CRC4 Multiframe.
0 = interrupt masked
1 = interrupt enabled
Transmit Side Elastic Store Slip Occurrence.
0 = interrupt masked
1 = interrupt enabled
44 of 117
TAF
LOTC
DS21354 & DS21554
(LSB)
RCMF
TSLIP

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