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DS21354 & DS21554
10.2 Hardware Based Signaling
10.2.1 Receive Side
In the receive side of the hardware based signaling, there are two operating modes for the signaling
buffer; signaling extraction and signaling re–insertion. Signaling extraction involves pulling the signaling
bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in
a serial PCM fashion on a channel–by–channel basis at the RSIG output. This mode is always enabled. In
this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then
the backplane clock (RSYSCLK) must be 2.048/4.096/8.192 MHz. The ABCD signaling bits are output
on RSIG in the lower nibble of each channel. The RSIG data is updated once a multiframe (2 ms) unless a
freeze is in effect. See the timing diagrams in Section 19.1 for some examples.
The other hardware based signaling operating mode called signaling re–insertion can be invoked by
setting the RSRE control bit high (CCR3.3 = 1). In this mode, the user will provide a multiframe sync at
the RSYNC pin and the signaling data be re–aligned at the RSER output according to this applied
multiframe boundary. in this mode, the elastic store must be enabled the backplane clock must be
2.048/4.096/8.192 MHz.
The signaling data in the two multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. To allow this freeze action to occur, the RFE
control bit (CCR2.0) should be set high. The user can force a freeze by setting the RFF control bit
(CCR2.1) high. Setting the RFF bit high causes the same freezing action as if a loss of synchronization,
carrier loss, or slip has occurred.
The 2 multiframe buffer provides an approximate 1 multiframe delay in the signaling bits provided at the
RSIG pin (and at the RSER pin if RSRE = 1 via CCR3.3). When freezing is enabled (RFE = 1), the
signaling data will be held in the last known good state until the corrupting error condition subsides.
When the error condition sub-sides, the signaling data will be held in the old state for an additional 3 ms
to 5 ms before being allowed to be updated with new signaling data.
10.2.2 Transmit Side
Via the THSE control bit (CCR3.2), the DS21354/554 can be set up to take the signaling data presented
at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER
pin. The hardware signaling insertion capabilities of each framer are available whether the transmit side
elastic store is enabled or disabled. If the transmit side elastic store is enabled, the backplane clock
(TSYSCLK) must be 2.048/4.096/8.192 MHz.
When hardware signaling insertion is enabled on a framer (THSE = 1), then the user must enable the
Transmit Channel Blocking Register Function Select (TCBFS) control bit (CCR3.6 = 1). This is needed
so that the CAS multiframe alignment word, multiframe remote alarm, and spare bits can be added to
timeslot 16 in frame 0 of the multiframe. The TS1 register should be programmed with the proper
information. If CCR3.6 = 1, then a zero in the TCBRs implies that signaling data is to be sourced from
TSER (or TSIG if CCR3.2 = 1) and a one implies that signaling data for that channel is to be sourced
from the Transmit Signaling (TS) registers. See definition below.
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