Dallas Semiconductor MAXIM DS21354 Manual
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Dallas Semiconductor MAXIM DS21354 Manual

3.3v/5v e1 single-chip transceivers
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GENERAL DESCRIPTION
The
DS21354/DS213554
(SCTs) contain all the necessary functions to connect to
E1 lines. The devices are upward-compatible versions
of the DS2153 and DS2154 SCTs. The on-board
clock/data recovery circuitry coverts the AMI/HDB3 E1
waveforms to an NRZ serial stream. Both devices
automatically adjust to E1 22AWG (0.6mm) twisted-
pair cables from 0 to over 2km in length. They can
generate the necessary G.703 waveshapes for both 75W
coax and 120W twisted cables. The on-board jitter
attenuator (selectable to either 32 bits or 128 bits) can
be placed in either the transmit or receive data paths.
The framer locates the frame and multiframe
boundaries and monitors the data stream for alarms. It is
also used for extracting and inserting signaling data, Si,
and Sa-bit information. The on-board HDLC controller
can be used for Sa-bit links or DS0s. The devices
contain a set of internal registers that the user can
access to control the operation of the units. Quick
access through the parallel control port allows a single
controller to handle many E1 lines. The devices fully
meet all the latest E1 specifications, including ITU-T
G.703, G.704, G.706, G.823, G.732, and I.431, ETS
300 011, 300 233, and 300 166, as well as CTR12 and
CTR4.
PIN CONFIGURATION
TOP VIEW
Semiconductor
DS21354/DS21554
100
1
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
3.3V/5V E1 Single-Chip Transceivers
single-chip
transceivers
Dallas
LQFP
FEATURES
§
Complete
Transceiver Functionality
§
On-Board Long- and Short-Haul Line Interface
for Clock/Data Recovery and Waveshaping
§
32-Bit or 128-Bit Crystal-Less Jitter Attenuator
§
Frames to FAS, CAS, CCS, and CRC4 Formats
§
Integral HDLC Controller with 64-Byte Buffers
Configurable for Sa Bits, DS0, or Sub-DS0
Operation
§
Dual Two-Frame Elastic Store Slip Buffers that
can Connect to Asynchronous Backplanes up to
8.192MHz
§
Interleaving PCM Bus Operation
§
8-Bit Parallel Control Port that can be used
Directly
Nonmultiplexed Buses (Intel or Motorola)
§
Extracts and Inserts CAS Signaling
§
Detects and Generates Remote and AIS Alarms
§
Programmable Output Clocks for Fractional E1,
H0, and H12 Applications
§
Fully
Independent
Functionality
§
Full Access to Si and Sa Bits Aligned with
CRC-4 Multiframe
§
Four Separate Loopback Functions for Testing
Functions
§
Large Counters for Bipolar and Code Violations,
CRC4 Codeword Errors, FAS Word Errors, and
E Bits
§
IEEE 1149.1 JTAG-Boundary Scan Architecture
§
Pin Compatible with DS2154/52/352/552 SCTs
§
3.3V (DS21354) or 5V (DS21554) Supply; Low-
Power CMOS
§
100-pin LQFP package (14mm x 14mm)
ORDERING INFORMATION
PART
DS21354L
DS21354LN
DS21554L
DS21554LN
1 of 124
DS21354/DS21554
E1
(CEPT)
PCM-30/ISDN-PRI
on
Either
Multiplexed
Transmit
and
TEMP RANGE
PIN-PACKAGE
0°C to +70°C
100 LQFP
-40°C to +85°C
100 LQFP
0°C to +70°C
100 LQFP
-40°C to +85°C
100 LQFP
or
Receive
REV: 021004

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  • Page 1 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers www.maxim-ic.com GENERAL DESCRIPTION FEATURES § DS21354/DS213554 single-chip transceivers Complete (CEPT) PCM-30/ISDN-PRI (SCTs) contain all the necessary functions to connect to Transceiver Functionality E1 lines. The devices are upward-compatible versions § On-Board Long- and Short-Haul Line Interface of the DS2153 and DS2154 SCTs.

  • Page 2: Table Of Contents

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TABLE OF CONTENTS 1. INTRODUCTION........................6 1.1. F ..........................7 UNCTIONAL ESCRIPTION 1.2. DOCUMENT REVISION HISTORY ......................8 2. BLOCK DIAGRAM ......................9 3. PIN DESCRIPTION......................10 3.1. PIN FUNCTION DESCRIPTION ........................14 3.1.1. Transmit-Side Pins..........................14 3.1.2. Receive-Side Pins..........................17 3.1.3.
  • Page 3 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 12. ELASTIC STORES OPERATION..................65 12.1. RECEIVE SIDE ............................65 12.2. TRANSMIT SIDE.............................65 13. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION ........66 13.1. HARDWARE SCHEME ...........................66 13.2. INTERNAL REGISTER SCHEME BASED ON DOUBLE FRAME ............66 13.3.
  • Page 4 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers LIST OF FIGURES Figure 2-1. DS21354/554 Block Diagram ..........................9 Figure 15-1. Basic External Analog Connections ......................83 Figure 15-2. Optional Crystal Connection........................... 83 Figure 15-3. Jitter Tolerance..............................84 Figure 15-4. Jitter Attenuation .............................. 84 Figure 15-5.
  • Page 5 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers LIST OF TABLES Table 3-1. Pin Description Sorted by Pin Number......................10 Table 3-2. Pin Description by Symbol ..........................12 Table 4-1. Register Map Sorted by Address ........................25 Table 5-1. Device ID Bit Map ..............................30 Table 5-2.

  • Page 6: Introduction

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 1. INTRODUCTION The DS21354/DS21554 are superset versions of the popular DS2153 and DS2154 SCTs offering the new features listed below. All the original features of the DS2153 and DS2154 have been retained, and the software created for the original devices is transferable into the DS21354/DS21554. New Features in the DS21354 and DS21554 FEATURE SECTION...

  • Page 7: Functional Description

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Functional Description 1.1. The analog AMI/HDB3 waveform off the E1 line is transformer coupled into the RRING and RTIP pins of the DS21354/554. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive-side framer where the digital serial stream is analyzed to locate the framing/multiframe pattern.

  • Page 8: Document Revision History

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Document Revision History 1.2. REVISION DESCRIPTION 012799 Initial release Corrected TSYSCLK and RSYSCLK timing and added 4.096MHz and 8.192MHz 012899 timing 020399 Corrected definition and label of TUDR bit in the THIR register. 021199 Corrected address of IBO register in text. 040199 Added Receive Monitor Mode section 041599...

  • Page 9: Block Diagram

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 2. BLOCK DIAGRAM Figure 2-1. DS21354/554 Block Diagram DS21354/ INT* DS21554 D0 to D7 / AD0 to AD7 A0 to A6 ALE(AS) / A7 RD*(DS*) WR*(R/W*) TEST Framer Loopback Remote Loopback TPOSO RPOSI TCLKO RCLKI TNEGO RNEGI TNEGI...

  • Page 10: Pin Description

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3. PIN DESCRIPTION Table 3-1. Pin Description Sorted by Pin Number NAME TYPE FUNCTION RCHBLK Receive Channel Block JTMS IEEE 1149.1 Test Mode Select 8MCLK 8.192 MHz Clock JTCLK IEEE 1149.1 Test Clock Signal IEEE 1149.1 Test Reset, Active Low JTRST Receive Carrier Loss JTDI...
  • Page 11 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers NAME TYPE FUNCTION TESO Transmit Elastic Store Output TDATA Transmit Data TSYSCLK Transmit System Clock TSSYNC Transmit System Sync TCHCLK Transmit Channel Clock Carry Out Bus Operation D0/AD0 Data Bus Bit0/Address/Data Bus Bit 0 D1/AD1 Data Bus Bit1/Address/Data Bus Bit 1 D2/AD2 Data Bus Bit 2/Address/Data Bus 2...

  • Page 12: Table 3-2. Pin Description By Symbol

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Table 3-2. Pin Description by Symbol NAME TYPE FUNCTION 8MCLK 8.192MHz Clock 8XCLK Eight-Times Clock Address Bus Bit 0 Address Bus Bit 1 Address Bus Bit 2 Address Bus Bit 3 Address Bus Bit 4 Address Bus Bit 5 Address Bus Bit 6 ALE (AS)/A7...
  • Page 13 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers NAME TYPE FUNCTION RLINK Receive Link Data RLOS/LOTC Receive Loss of Sync/Loss of Transmit Clock RMSYNC Receive Multiframe Sync RNEGI Receive Negative Data Input RNEGO Receive Negative Data Output RPOSI Receive Positive Data Input RPOSO Receive Positive Data Output RRING Receive Analog Ring Input...

  • Page 14: Pin Function Description

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Pin Function Description 3.1. 3.1.1. Transmit-Side Pins Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input...
  • Page 15 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into any combination of the Sa bit positions (Sa4 to Sa8). See Section for details.
  • Page 16 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Signal Name: TNEGO Signal Description: Transmit Negative Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally tied to TNEGI. Signal Name: TCLKO Signal Description:...

  • Page 17: Receive-Side Pins

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1.2. Receive-Side Pins Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output Updated with the fully recovered E1 data stream on the rising edge of RCLK. Signal Name: RLCLK Signal Description: Receive Link Clock Signal Type: Output 4kHz to 20kHz clock (Sa bits) for the RLINK output.
  • Page 18 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Signal Name: RFSYNC Signal Description: Receive Frame Sync Signal Type: Output An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries. Signal Name: RMSYNC Signal Description: Receive Multiframe Sync Signal Type: Output If the receive-side elastic store is enabled, an extracted pulse, one RSYSCLK wide, is output at this pin...
  • Page 19 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Signal Name: 8MCLK Signal Description: 8MHz Clock Signal Type: Output An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin. Signal Name: RPOSO Signal Description: Receive Positive Data Input Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface.

  • Page 20: Parallel Control Port Pins

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1.3. Parallel Control Port Pins Signal Name: Signal Description: Interrupt Signal Type: Output Active-low, open-drain output that flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the HDLC Status Register. Signal Name: Signal Description: Framer Mode Select...
  • Page 21 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Signal Name: RD (DS) Signal Description: Read Input—Data Strobe Signal Type: Input In Intel Mode, RD determines when data is read from the device. In Motorola Mode, DS is used to write to the device. See the Bus Timing Diagrams section. Signal Name: Signal Description: Chip Select...

  • Page 22: Jtag Test Access Port Pins

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1.4. JTAG Test Access Port Pins JTRST Signal Name: Signal Description: IEEE 1149.1 Test Reset Signal Type: Input This signal is used to asynchronously reset the test access port controller. At power up, JTRST must be toggled from low to high.

  • Page 23: Line Interface Pins

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1.6. Line Interface Pins Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. A quartz crystal of 2.048MHz may be applied across MCLK and XTALD instead of the TTL level clock source.

  • Page 24: Supply Pins

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1.7. Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 5.0V ±5% (DS21554) or 3.3V ±5% (DS21354). Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply...

  • Page 25: Parallel Port

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 4. PARALLEL PORT The DS21354/DS21554 are controlled through either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing is selected; if tied high, Motorola timing is selected.
  • Page 26 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers ADDRESS TYPE REGISTER NAME Transmit Channel Blocking 4 TCBR4 Transmit Idle 1 TIR1 Transmit Idle 2 TIR2 Transmit Idle 3 TIR3 Transmit Idle 4 TIR4 Transmit Idle Definition TIDR Receive Channel Blocking 1 RCBR1 Receive Channel Blocking 2 RCBR2 Receive Channel Blocking 3 RCBR3...
  • Page 27 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers ADDRESS TYPE REGISTER NAME Transmit Sa6 Bits TSa6 Transmit Sa7 Bits TSa7 Transmit Sa8 Bits TSa8 Receive Si Bits Align Frame RSiAF Receive Si Bits Non-Align Frame RSiNAF Receive Remote Alarm Bits Receive Sa4 Bits RSa4 Receive Sa5 Bits RSa5...
  • Page 28 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers ADDRESS TYPE REGISTER NAME Receive Channel 6 Receive Channel 7 Receive Channel 8 Receive Channel 9 Receive Channel 10 RC10 Receive Channel 11 RC11 Receive Channel 12 RC12 Receive Channel 13 RC13 Receive Channel 14 RC14 Receive Channel 15 RC15...
  • Page 29 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers ADDRESS TYPE REGISTER NAME Interleave Bus Operation Register Transmit HDLC Information Register THIR Transmit HDLC FIFO Register THFR Receive HDLC DS0 Control Register 1 RDC1 Receive HDLC DS0 Control Register 2 RDC2 Transmit HDLC DS0 Control Register 1 TDC1 Transmit HDLC DS0 Control Register 2 TDC2...

  • Page 30: Control, Id, And Test Registers

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 5. CONTROL, ID, AND TEST REGISTERS The operation of the DS21354/DS21554 is configured via a set of 10 control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers need only to be accessed when there is a change in the system configuration.
  • Page 31 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex) (MSB) (LSB) T1E1 Bit 6 Bit 5 Bit 4 SYMBOL POSITION NAME AND DESCRIPTION T1 or E1 Chip Determination Bit. Set to 1. T1E1 IDR.7 0 = T1 chip 1 = E1 chip Bit 6 IDR.6...

  • Page 32: Synchronization And Resynchronization

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Synchronization And Resynchronization 5.2. Once synchronization is accomplished there are certain criteria that can cause a resynchronization. These criteria are detailed in Table 5-2. Also see Figure 18-14 for a flow chart of the synchronization process. Table 5-2.
  • Page 33 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex) (MSB) (LSB) Sa8S Sa7S Sa6S Sa5S Sa4S RBCS RESE — SYMBOL POSITION NAME AND DESCRIPTION Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit position; Sa8S RCR2.7 set to zero to force RLCLK low during Sa8 bit position.
  • Page 34 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex) (MSB) (LSB) TFPT T16S TUA1 TSiS TSA1 TSIO SYMBOL POSITION NAME AND DESCRIPTION Output Data Format. TCR1.7 0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO=0 Transmit Time Slot 0 Pass Through.
  • Page 35 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex) (MSB) (LSB) Sa8S Sa7S Sa6S Sa5S Sa4S AEBE SYMBOL POSITION NAME AND DESCRIPTION Sa8 Bit Select. Set to one to source the Sa8 bit from the TLINK pin; set Sa8S TCR2.7 to zero to not source the Sa8 bit.

  • Page 36: Framer Loopback

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex) (MSB) (LSB) THDB3 TG802 TCRC4 RHDB3 RG802 RCRC4 SYMBOL POSITION NAME AND DESCRIPTION Framer Loopback. CCR1.7 0 = loopback disabled 1 = loopback enabled Transmit HDB3 Enable. THDB3 CCR1.6 0 = HDB3 disabled...
  • Page 37 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex) (MSB) (LSB) ECUS VCRFS AAIS RSERC LOTCMC SYMBOL POSITION NAME AND DESCRIPTION Error Counter Update Select. See Section for details. ECUS CCR2.7 0 = update error counters once a second 1 = update error counters every 62.5ms (500 frames) VCR Function Select.

  • Page 38: Automatic Alarm Generation

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Automatic Alarm Generation 5.4. The device can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive-side framer to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal).
  • Page 39 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex) (MSB) (LSB) TESE TCBFS TIRFS — RSRE THSE TBCS RCLA SYMBOL POSITION NAME AND DESCRIPTION Transmit-Side Elastic Store Enable. TESE CCR3.7 0 = elastic store is bypassed 1 = elastic store is enabled Transmit Channel Blocking Registers (TCBR) Function Select.

  • Page 40: Remote Loopback

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR4: COMMON CONTROL REGISTER 4 (Address = A8 Hex) (MSB) (LSB) LIAIS TCM4 TCM3 TCM2 TCM1 TCM0 SYMBOL POSITION NAME AND DESCRIPTION Remote Loopback. CCR4.7 0 = loopback disabled 1 = loopback enabled Local Loopback. CCR4.6 0 = loopback disabled 1 = loopback enabled...
  • Page 41 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex) (MSB) (LSB) LIRST RESA TESA RCM4 RCM3 RCM2 RCM1 RCM0 SYMBOL POSITION NAME AND DESCRIPTION Line Interface Reset. Setting this bit from a zero to a one will initiate an internal reset that affects the clock recovery state machine and jitter LIRST CCR5.7...
  • Page 42 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR6: COMMON CONTROL REGISTER 6 (Address = 1D Hex) (MSB) (LSB) LIUODO CDIG LIUSI — — TCLKSRC RESR TESR SYMBOL POSITION NAME AND DESCRIPTION Line Interface Open-Drain Option. This control bit determines whether the TTIP and TRING outputs will be open drain or not. The line driver outputs can be forced open drain to allow 6Vpeak pulses to be generated LIUODO CCR6.7...

  • Page 43: Status And Information Registers

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 6. STATUS AND INFORMATION REGISTERS The DS21354/DS21554 have a set of seven registers that contain information on the current real-time status of a framer—Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), Synchronizer Status Register (SSR), and a set of three registers for the on-board HDLC controller.
  • Page 44 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex) (MSB) (LSB) TESF TESE JALT RESF RESE CRCRC FASRC CASRC SYMBOL POSITION NAME AND DESCRIPTION Transmit-Side Elastic Store Full. Set when the transmit-side elastic TESF RIR.7 store buffer fills and a frame is deleted. Transmit-Side Elastic Store Empty.

  • Page 45: Crc4 Sync Counter

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CRC4 Sync Counter 6.1. The CRC4 Sync Counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (CCR1.0 = 0).

  • Page 46: Table 6-1. Alarm Criteria

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Table 6-1. Alarm Criteria ALARM SET CRITERIA CLEAR CRITERIA ITU SPEC. over 16 consecutive frames over 16 consecutive frames G.732 RSA1 (one full MF) time slot 16 (one full MF) time slot 16 (Receive Signaling All contains less than three contains three or more Ones)
  • Page 47 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers SR2: STATUS REGISTER 2 (Address = 07 Hex) (MSB) (LSB) LOTC RCMF TSLIP SYMBOL POSITION NAME AND DESCRIPTION Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is SR2.7 enabled or not) on receive multiframe boundaries. Used to alert the host that signaling data is available.
  • Page 48 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers IMR1: INTERRUPT MASK REGISTER 1 (Address = 16 Hex) (MSB) (LSB) RSA1 RDMA RSA0 RSLIP RUA1 RLOS SYMBOL POSITION NAME AND DESCRIPTION Receive Signaling All Ones/Signaling Change. RSA1 IMR1.7 0 = interrupt masked 1 = interrupt enabled Receive Distant MF Alarm.
  • Page 49 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers IMR2: INTERRUPT MASK REGISTER 2 (Address = 17 Hex) (MSB) (LSB) LOTC RCMF TSLIP SYMBOL POSITION NAME AND DESCRIPTION Receive CAS Multiframe. IMR2.7 0 = interrupt masked 1 = interrupt enabled Receive Align Frame. IMR2.6 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe.

  • Page 50: Error Count Registers

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 7. ERROR COUNT REGISTERS The DS21354/DS21554 have a set of four counters that record bipolar or code violations, errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. Each of these four counters is automatically updated on either one-second boundaries (CCR2.7 = 0) or every 62.5ms (CCR2.7 = 1) as determined by the timer in Status Register 2 (SR2.4).

  • Page 51: Crc4 Error Counter

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CRC4 Error Counter 7.2. CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the maximum CRC4 count in a one second period is 1000, this counter cannot saturate.

  • Page 52: Fas Error Counter

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers FAS Error Counter 7.4. FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 12–bit counter that records word errors in the Frame Alignment Signal in time slot 0. This counter is disabled when RLOS is high.

  • Page 53: Ds0 Monitoring Function

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 8. DS0 MONITORING FUNCTION Each framer in the DS21354/DS21554 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4 register.
  • Page 54 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address = A9 Hex) (MSB) (LSB) SYMBOL POSITION NAME AND DESCRIPTION Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be TDS0M.7 transmitted). TDS0M.6 Transmit DS0 Channel Bit 2. TDS0M.5 Transmit DS0 Channel Bit 3.
  • Page 55 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RDS0M: RECEIVE DS0 MONITOR REGISTER (Address = AB Hex) (MSB) (LSB) SYMBOL POSITION NAME AND DESCRIPTION RDS0M.7 Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received). RDS0M.6 Receive DS0 Channel Bit 2. RDS0M.5 Receive DS0 Channel Bit 3.

  • Page 56: Signaling Operation

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 9. SIGNALING OPERATION The DS21354/DS21554 contain provisions for both processor-based (i.e., software-based) signaling bit access and for hardware-based access. Both the processor-based access and the hardware-based access can be used simultaneously if necessary. The processor-based signaling is covered in Section and the hardware based signaling is covered in Section 9.2.
  • Page 57 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two time slots. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits.

  • Page 58: Hardware-Based Signaling

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers the TSRs before the old data is retransmitted. ITU specifications recommend that the ABCD signaling not be set to all zeros because they will emulate a CAS multiframe alignment word. The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble. The upper nibble must always be set to 0000 or else the terminal at the far end loses multiframe synchronization.

  • Page 59: Transmit Side

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 9.2.2. Transmit Side Via the THSE control bit (CCR3.2), the DS21354/DS21554 can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin.

  • Page 60: Per-Channel Code Generation And Loopback

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers PER-CHANNEL CODE GENERATION AND LOOPBACK The DS21354/DS21554 can replace data on a channel-by-channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section 10.1. The receive direction is from the E1 line to the backplane and is covered in Section 10.2.

  • Page 61: Per-Channel Code Insertion

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex) (MSB) (LSB) TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 TIDR1 TIDR0 SYMBOL POSITION NAME AND DESCRIPTION TIDR7 TIDR.7 MSB of the Idle Code (this bit is transmitted first) TIDR0 TIDR.0 LSB of the Idle Code (this bit is transmitted last)

  • Page 62: Receive-Side Code Generation

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Receive-Side Code Generation 10.2. On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the code placed in the Receive Channel Registers (RC1 to RC32).

  • Page 63: Clock Blocking Registers

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CLOCK BLOCKING REGISTERS The receive-channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit-channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins, respectively. (The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD controller in ISDN–PRI applications.
  • Page 64 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1 (MSB) (LSB) CH18 CH17 CH16 TCBR1(22) CH22 CH21 CH20 CH19 TCBR2(23) CH26 CH11 CH25 CH10 CH24 CH23 TCBR3(24) CH30 CH15 CH29 CH14 CH28 CH13 CH27 CH12 TCBR4(25) *These bits should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm bits. 64 of 124...

  • Page 65: Elastic Stores Operation

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers ELASTIC STORES OPERATION The DS21354/DS21554 contain dual two-frame (512 bits) elastic stores, one for the receive direction and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the E1 data stream to 1.544Mbps (or a multiple of 1.544Mbps), which is the T1 rate.

  • Page 66: Additional (Sa) And International (Si) Bit Operation

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION The DS21354/DS21554 provide for access to both the Sa and the Si bits through three different methods. The first method is accomplished via a hardware scheme using the RLINK/RLCLK and TLINK/TLCLK pins (see Section 13.1).
  • Page 67 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RAF: RECEIVE ALIGN FRAME REGISTER (Address = 2F Hex) (MSB) (LSB) SYMBOL POSITION NAME AND DESCRIPTION RAF.7 International Bit. RAF.6 Frame Alignment Signal Bit. RAF.5 Frame Alignment Signal Bit. RAF.4 Frame Alignment Signal Bit. RAF.3 Frame Alignment Signal Bit.

  • Page 68: Internal Register Scheme Based On Crc4 Multiframe

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address = 21 Hex) (MSB) (LSB) SYMBOL POSITION NAME AND DESCRIPTION TNAF.7 International Bit. TNAF.6 Frame Non-Alignment Signal Bit. TNAF.5 Remote Alarm (used to transmit the alarm). TNAF.4 Additional Bit 4. TNAF.3 Additional Bit 5.
  • Page 69 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TSaCR: TRANSMIT Sa BIT CONTROL REGISTER (Address = 1C Hex) (MSB) (LSB) SiAF SiNAF SYMBOL POSITION NAME AND DESCRIPTION International Bit in Align Frame Insertion Control Bit. 0 = do not insert data from the TSiAF register into the transmit data SiAF TSaCR.7 stream...

  • Page 70: Hdlc Controller For The Sa Bits Or Ds0

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers HDLC CONTROLLER FOR THE Sa BITS OR DS0 The DS21354/DS21554 can extract/insert data from/into the Sa bit positions (Sa4 to Sa8) or from/to any multiple of DS0 or sub-DS0 channels. The SCT contains a complete HDLC controller (see Section 14). General Overview 14.1.

  • Page 71: Hdlc Status Registers

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers HDLC Status Registers 14.2. Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one.

  • Page 72: Basic Operation Details

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Basic Operation Details 14.3. As a basic guideline for interpreting and sending HDLC messages, the following sequences can be applied: 14.3.1. Example: Receive an HDLC Message 1. Enable RPS interrupts 2. Wait for interrupt to occur 3.

  • Page 73: Hdlc Register Description

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers HDLC Register Description 14.4. HCR: HDLC CONTROL REGISTER (Address = B0 Hex) (MSB) (LSB) — TABT TEOM TZSD TCRCD SYMBOL POSITION NAME AND DESCRIPTION — HCR.7 Not Assigned. Should be set to zero when written. Receive HDLC Reset.
  • Page 74 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers HSR: HDLC STATUS REGISTER (Address = B1 Hex) (MSB) (LSB) FRCL RHALF THALF TMEND SYMBOL POSITION NAME AND DESCRIPTION Framer Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0 = 1) FRCL HSR.7 consecutive zeros have been detected at RPOSI and RNEGI. Receive Packet End.
  • Page 75 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers HIMR: HDLC INTERRUPT MASK REGISTER (Address = B2 Hex) (MSB) (LSB) FRCL RHALF THALF TMEND SYMBOL POSITION NAME AND DESCRIPTION Framer Receive Carrier Loss. FRCL HIMR.7 0 = interrupt masked 1 = interrupt enabled Receive Packet End. HIMR.6 0 = interrupt masked 1 = interrupt enabled...
  • Page 76 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = B3 Hex) (MSB) (LSB) RABT RCRCE ROVR REMPTY CBYTE OBYTE SYMBOL POSITION NAME AND DESCRIPTION Abort Sequence Detected. Set whenever the HDLC controller sees 7 or RABT RHIR.7 more ones in a row.
  • Page 77 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers THIR: TRANSMIT HDLC INFORMATION REGISTER (Address = B6 Hex) (MSB) (LSB) — — — — — TEMPTY TFULL TUDR SYMBOL POSITION NAME AND DESCRIPTION — THIR.7 Not Assigned. Could be any value when read. — THIR.6 Not Assigned.
  • Page 78 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RDC1: RECEIVE HDLC DS0 CONTROL REGISTER 1 (Address = B8 Hex) (MSB) (LSB) RSaDS RDS0M SYMBOL POSITION NAME AND DESCRIPTION Receive HDLC source RDC1.7 0 = Sa bits defined by RCR2.3 to RCR2.7. 1 = Sa bits or DS0 channels defined by RDC1 (see bits defined below). Receive Sa Bit/DS0 Select.
  • Page 79 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address = BA Hex) (MSB) (LSB) TSaDS TDS0M SYMBOL POSITION NAME AND DESCRIPTION Transmit HDLC Enable. 0 = disable HDLC controller (no data inserted by HDLC controller into the transmit data stream) TDC1.7 1 = enable HDLC controller to allow insertion of HDLC data into either...

  • Page 80: Line Interface Functions

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers LINE INTERFACE FUNCTIONS The line interface function in the DS21354/DS21554 contains three sections: (1) the receiver, which handles clock and data recovery; (2) the transmitter, which waveshapes and drives the E1 line; and (3) the jitter attenuator.

  • Page 81: Receive Clock And Data Recovery

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Receive Clock and Data Recovery 15.1. The DS21354/DS21554 contain a digital clock recovery system. See Figure 2-1 Figure 15-1 for more details. The device couples to the receive-E1-shielded twisted pair or coax via a 1:1 transformer. See Table 15-3 for transformer details.

  • Page 82: Jitter Attenuator

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Table 15-2. Line Build-Out Select in LICR for the DS21354 APPLICATION TRANSFORMER RETURN LOSS (dB) RT (W) 1:2 step-up N.M. 75W normal 1:2 step-up N.M. 120W normal 1:2 step-up N.M. 75W with protection resistors 1:2 step-up N.M.

  • Page 83: Figure 15-1. Basic External Analog Connections

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 15-1. Basic External Analog Connections 0.47 (nonpolarized) DS21354/DS21554 DVDD TTIP E1 Transmit 0.01 Line TRING DVSS N : 1 RVDD (See Note 1) RVSS 1 : 1 TVDD RTIP E1 Receive TVSS Line RRING MCLK 2.048MHz 0.1mF...

  • Page 84: Figure 15-3. Jitter Tolerance

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 15-3. Jitter Tolerance DS21354/ DS21554 Tolerance Minimum Tolerance Level as per ITU G.823 2.4K 100K FREQUENCY (Hz) Figure 15-4. Jitter Attenuation ITU G.7XX Prohibited Area -20dB ETS 300 011 & TBR12 Prohibited Area -40dB -60dB 100K FREQUENCY (Hz)

  • Page 85: Figure 15-5. Transmit Waveform Template

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 15-5. Transmit Waveform Template 269ns G.703 194ns Template 219ns -0.1 -0.2 -250 -200 -150 -100 TIME (ns) 85 of 124...

  • Page 86: Protected Interfaces

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Protected Interfaces 15.4. In certain applications, such as connecting to the PSTN, it is required that the network interface be protected from and resistant to certain electrical conditions. These conditions are divided into two categories, surge and power line cross. A typical cause of surge is lightening strike. Power-line cross refers to accidental contact with high-voltage power wiring.

  • Page 87: Figure 15-6. Protected Interface Example For The Ds21554

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 15-6. Protected Interface Example for the DS21554 DS21554 +5.0V Fuse TTIP DVDD Transmit 0.01 Line DVSS TRING Fuse RVDD RVSS Fuse TVDD RTIP Receive TVSS Line RRING Fuse MCLK 2.048MHz Rterm Rterm NOTE 1: ALL CAPACITOR VALUES ARE IN mF. NOTE 2: THE 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION.

  • Page 88: Figure 15-7. Protected Interface Example For The Ds21354

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 15-7. Protected Interface Example for the DS21354 +3.3V DS21354 +3.3V Fuse TTIP DVDD Transmit 0.01 Line DVSS TRING Fuse RVDD RVSS Fuse TVDD RTIP Receive TVSS Line RRING Fuse MCLK 2.048MHz 37/60 37/60 NOTE 1: ALL CAPACITOR VALUES ARE IN mF. NOTE 2: THE 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION.

  • Page 89: Receive Monitor Mode

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Receive Monitor Mode 15.5. When connecting to a monitor port, a large resistive loss is incurred due to the voltage divider between the E1 line termination resistors (Rt) and the monitor port isolation resistors (Rm), as shown in Figure 15-8.

  • Page 90: Jtag Boundary Scan Architecture And Test Access Port

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT DS21354/DS21554 IEEE 1149.1 design supports standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Figure 16-1. The device contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.

  • Page 91: Figure 16-1. Jtag Functional Block Diagram

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 16-1. JTAG Functional Block Diagram BOUNDARY SCAN REGISTER IDENTIFICATION REGISTER BYPASS REGISTER INSTRUCTION REGISTER SELECT TEST ACCESS OUTPUT ENABLE PORT 10kW 10kW 10kW JTDO JTRST JTDI JTMS JTCLK 91 of 124...
  • Page 92 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 16-2. Test-Logic-Reset Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction.
  • Page 93 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state.

  • Page 94: Figure 16-2. Tap Controller State Diagram

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 16-2. TAP Controller State Diagram Test Logic Reset Run Test/ Select Select Idle DR-Scan IR-Scan Capture DR Capture IR Shift DR Shift IR Exit DR Exit IR Pause DR Pause IR Exit2 DR Exit2 IR Update DR Update IR 94 of 124...

  • Page 95: Instruction Register

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Instruction Register 16.1. The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO.

  • Page 96: Test Registers

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The ID code will always have a one in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version.

  • Page 97: Table 16-4. Boundary Scan Control Bits

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Table 16-4. Boundary Scan Control Bits NAME TYPE NAME TYPE NAME TYPE RCHBLK — JTMS TSYNC. cntl — — (Note 1) 8MCLK TSYNC (AS)/A7 — JTCLK TPOSI RD ( DS ) — JTRST TNEGI TCLKI —...

  • Page 98: Interleaved Pcm Bus Operation

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers INTERLEAVED PCM BUS OPERATION In many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. The DS21354/DS21554 can be configured to allow data and signaling buses to be multiplexed into higher speed data and signaling buses eliminating external hardware saving board space and cost.

  • Page 99: Channel Interleave

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 17-1. IBO Basic Configuration Using Four SCTs RSYSCLK RSYSCLK TSYSCLK TSYSCLK RSYNC RSYNC TSSYNC TSSYNC MASTER SLAVE #2 RSIG RSIG TSIG TSIG TSER TSER RSER RSER 8.192MHz System Clock In System 8KHz Frame Sync In PCM Signaling Out PCM Signaling In PCM Data In...

  • Page 100: Functional Timing Diagrams

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers FUNCTIONAL TIMING DIAGRAMS Receive 18.1. Figure 18-1. Receive-Side Timing FRAM E# 10 11 12 13 14 15 16 1 RFSYNC RSYNC RSYNC RLCLK RLINK NOTE 1: RSYNC IN FRAME MODE (RCR1.6 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (RCR1.6 = 1). NOTE 3: RLCLK IS PROGRAMMED TO OUTPUT JUST THE SA BITS.

  • Page 101: Figure 18-3. Receive-Side 1.544Mhz Boundary Timing (With Elastic Store Enabled)

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) RSYSCLK CHANNEL 23/31 CHANNEL 24/32 CHANNEL 1/2 RSER RSYNC RMSYNC RSYNC RCHCLK RCHBLK NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS (MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ON1).

  • Page 102: Figure 18-5. Receive-Side Interleave Bus Operation, Byte Mode

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-5. Receive-Side Interleave Bus Operation, Byte Mode RSYNC R SER FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 R SIG FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1...

  • Page 103: Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-6. Receive-Side Interleave Bus Operation, Frame Mode RSYNC FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 R S E R FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 R S IG R S E R FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 R S IG...

  • Page 104: Transmit

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Transmit 18.2. Figure 18-7. Transmit-Side Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 14 15 16 TSYNC TSSYNC TSYNC...

  • Page 105: Figure 18-9. Transmit-Side 1.544Mhz Boundary Timing (With Elastic Store Enabled)

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) TSYSCLK CHANNEL 23 CHANNEL 24 CHANNEL 1 TSER LSB MSB F MSB TSSYNC TCHCLK TCHBLK NOTE 1: THE F-BIT POSITION IN THE TSER DATA IS IGNORED. NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24.

  • Page 106: Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-11. Transmit-Side Interleave Bus Operation, Byte Mode TSYNC TSER FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 TSIG FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1...

  • Page 107: Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-12. Transmit-Side Interleave Bus Operation, Frame Mode TSYNC FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 TSER FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 TSIG TSER FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 TSIG FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL...

  • Page 108: Figure 18-13. G.802 Timing

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-13. G.802 Timing TS # 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RSYNC TSYNC RCHCLK...

  • Page 109: Figure 18-14. Ds21354/Ds21554 Framer Synchronization Flowchart

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-14. DS21354/DS21554 Framer Synchronization Flowchart Power Up RLOS = 1 FAS Search FASSA = 1 RLOS = 1 FAS Sync Criteria Met Resync if FASSA = 0 RCR1.1 = 0 Increment CRC4 CRC4 Multiframe Search CAS Multiframe Search Sync Counter;...

  • Page 110: Figure 18-15. Ds21354/Ds21554 Transmit Data Flow

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-15. DS21354/DS21554 Transmit Data Flow TS ER H D LC & E N G IN E TD A TA TN AF.0-4 S a Data Source D S0 D ata M U X Source M U X (TD C 1) (TD C1/2) R S E R...

  • Page 111: Operating Parameters

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………………-1.0V to +6.0V Operating Temperature Range for DS21354L/DS21554L……………………………………………………0°C to +70°C Operating Temperature Range for DS21354LN/DS21554LN……………………………………………..-40°C to +85°C Storage Temperature Range………………………………………………………………………………...-55°C to +125°C Soldering Temperature………………………………………………………..See IPC/JEDEC J-STD-020A Specification This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.

  • Page 112: Ac Timing Parameters And Diagrams

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers AC TIMING PARAMETERS AND DIAGRAMS Multiplexed Bus AC Characteristics 20.1. AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT (MUX = 1) = 3.3V ± 5%, T = 0°C to +70°C; for DS21354L; V = 5.0V ±5% , T = 0°C to +70°C for DS21554L; = 3.3V ±...

  • Page 113: Figure 20-1. Intel Bus Read Ac Timing (Bts = 0/Mux = 1)

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-1. Intel Bus Read Ac Timing (BTS = 0/MUX = 1) t CYC t ASD ASED t ASD t DDR AD0–AD7 Figure 20-2. Intel Bus Write Timing (BTS = 0/MUX = 1) t CYC t ASD ASED t ASD...

  • Page 114: Figure 20-3. Motorola Bus Ac Timing (Bts = 1/Mux = 1)

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-3. Motorola Bus AC Timing (BTS = 1/MUX = 1) PW EH t ASED t ASD PW EL t CYC t RWS AD0–AD7 (READ) t CH t CS t ASL AD0–AD7 (WRITE) 114 of 124...

  • Page 115: Nonmultiplexed Bus Ac Characteristics

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Nonmultiplexed Bus AC Characteristics 20.2. AC CHARACTERISTICS—NONMULTIPLEXED PARALLEL PORT (MUX = 0) = 3.3V ± 5%, T = 5.0V ±5% , T = 0°C to +70°C; for DS21354L; V = 0°C to +70°C for DS21554L; = 3.3V ±...

  • Page 116: Figure 20-5. Intel Bus Write Ac Timing (Bts = 0/Mux = 0)

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-5. Intel Bus Write AC Timing (BTS = 0/MUX = 0) A0–A7 ADDRESS VALID D0–D7 10ns 10ns 0ns MIN 0ns MIN 0ns MIN 75ns MIN Figure 20-6. Motorola Bus Read AC Timing (BTS = 1/MUX = 0) ADDRESS VALID A0–A7 DATA VALID...

  • Page 117: Receive-Side Ac Characteristics

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Receive-Side AC Characteristics 20.3. AC CHARACTERISTICS—RECEIVE SIDE = 3.3V ± 5%, T = 5.0V ±5% , T = 0°C to +70°C; for DS21354L; V = 0°C to +70°C for DS21554L; = 3.3V ± 5%, T = -40°C to +85°C for DS21354LN;...

  • Page 118: Figure 20-8. Receive-Side Ac Timing

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-8. Receive-Side AC Timing RCLK t D1 MSB of Channel 1 RSER / RDATA / RSIG t D2 RCHCLK t D2 RCHBLK RFSYNC / RMSYNC t D2 RSYNC t D2 RLCLK t D1 Sa4 to Sa8 Bit Position RLINK Notes:...

  • Page 119: Figure 20-9. Receive System Side Ac Timing

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-9. Receive System Side AC Timing RSYSCLK t SP t D3 MSB of Channel 1 RSER / RSIG t D4 RCHCLK t D4 RCHBLK RMSYNC / CO t D4 RSYNC t SU RSYNC t WC t SC Notes: 1.

  • Page 120: Figure 20-10. Receive Line Interface Ac Timing

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-10. Receive Line Interface AC Timing RCLKO t LP t DD RPOSO, RNEGO RCLKI t CP t SU RPOSI, RNEGI t HD 120 of 124...

  • Page 121: Transmit Ac Characteristics

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Transmit AC Characteristics 20.4. AC CHARACTERISTICS—TRANSMIT SIDE = 3.3V ± 5%, T = 5.0V ±5% , T = 0°C to +70°C; for DS21354L; V = 0°C to +70°C for DS21554L; = 3.3V ± 5%, T = -40°C to +85°C for DS21354LN;...

  • Page 122: Figure 20-11. Transmit-Side Ac Timing

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-11. Transmit-Side AC Timing TCLK TESO t SU TSER / TSIG / TDATA t HD t D2 TCHCLK t D2 TCHBLK t D2 TSYNC TSYNC TLCLK TLINK Notes: 1. TSYNC is in the output mode (TCR1.0 = 1). 2.

  • Page 123: Figure 20-12. Transmit System Side Ac Timing

    DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-12. Transmit System Side AC Timing TSYSCLK TSER t D3 t HD TCHCLK / CO t D3 TCHBLK t SU TSSYNC t WC t SC Notes: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2.

  • Page 124: Package Information

    Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

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