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Dallas Semiconductor DS21354LN Manual (117 pages)

E1 Single Chip Transceivers;

Brand: Dallas Semiconductor | Category: Transceiver | Size: 0 MB

Table of Contents
2
1 List of Figures

5
2 List of Tables

6
3 Introduction

7
- Functional Description
  8
- Document Revision History
  9
4 Pin Description

11
- Pin Function Description
  15
  - Transmit Side Pins
    15
  - Receive Side Pins
    18
  - Parallel Control Port Pins
    20
  - JTAG Test Access Port Pins
    22
  - Interleave Bus Operation Pins
    23
  - Line Interface Pins
    23
  - Supply Pins
    24
5 Parallel Port

24
- Register Map
  25
6 Control, ID, and Test Registers

29
- Power-Up Sequence
  30
  - Synchronizatrion and Re-Synchronization
    31
- Framer Loopback
  34
- Automatic Alarm Generation
  35
- Remote Loopback
  37
- Local Loopback
  37
7 Status and Information Registers

39
- CRC4 Sync Counter
  41
8 Error Count Registers

44
- BPV or Code Violation Counter
  44
- CRC4 Error Counter
  45
- E-Bit Counter
  45
- FAS Error Counter
  46
9 Ds0 Monitoring Function

46
10 Signaling Operation

48
- Processor Based Signaling
  48
  - Hardware Based Signaling
    51
    
    Receive Side
    51
    
    Transmit Side
    51
11 Per-Channel Code Generation and Loopback

52
- Transmit Side Code Generation
  52
  - Simple Idle Code Insertion and Per-Channel Loopback
    52
  - Per-Channel Code Insertion
    53
- Receive Side Code Generation
  54
12 Clock Blocking Registers

54
13 Elastic Stores Operation

56
- Receive Side
  56
- Transmit Side
  56
14 Additional (Sa) and International (Si) Bit Operation

56
15 Hdlc Controller for the Sa Bits or Ds0

60
- General Overview
  60
- HDLC Status Registers
  61
- Basic Operation Details
  62
  - Receive a HDLC Message
    62
  - Transmit an HDLC Message
    62
- HDLC Register Description
  63
16 Line Interface Functions

68
- Receive Clock and Data Recovery
  69
- Transmit Waveshaping and Line Driving
  69
- Jitter Attenuator
  71
- Protected Interfaces
  74
- Receive Monitor Mode
  76
17 Jtag-Voundary Scan Architecture and Test Access Port

77
- Description
  77
- TAP Controller State Machine
  78
- Instruction Register
  81
- Test Registers
  83
18 Interleaved Pcm Bus Operation

86
- Channel Interleave
  87
- Frame Interleave
  87
19 Functional Timing Diagrams

88
- Receive
  88
- Transmit
  94
20 Operating Parameters

103
21 Ac Timing Parameters and Diagrams

104
22 Mechanical Description

117

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Dallas Semiconductor DS21354LN Telecom Manuals

Dallas Semiconductor DS21354LN Manual (117 pages)

Table of Contents

1 List of Figures

2 List of Tables

3 Introduction

4 Pin Description

5 Parallel Port

6 Control, ID, and Test Registers

7 Status and Information Registers

8 Error Count Registers

9 Ds0 Monitoring Function

10 Signaling Operation

11 Per-Channel Code Generation and Loopback

12 Clock Blocking Registers

13 Elastic Stores Operation

14 Additional (Sa) and International (Si) Bit Operation

15 Hdlc Controller for the Sa Bits or Ds0

16 Line Interface Functions

17 Jtag-Voundary Scan Architecture and Test Access Port

18 Interleaved Pcm Bus Operation

19 Functional Timing Diagrams

20 Operating Parameters

21 Ac Timing Parameters and Diagrams

22 Mechanical Description

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