Receive Side Code Generation; Clock Blocking Registers - Dallas Semiconductor DS21354L Manual

TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER
(Address=A0 to A3 Hex)
(MSB)
CH8 CH7
CH16 CH15
CH24 CH23
CH32 CH31
SYMBOL POSITION
CH 1 - 32 TCC1.0 - 4.7 Transmit Channel Code Insertion Control Bits

11.2 Receive Side Code Generation

On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of
the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the code
placed in the Receive Channel Registers (RC1 to RC32). This method allows a different 8–bit code to be
placed into each of the 32 E1 channels.
RC1 TO RC32: RECEIVE CHANNEL REGISTERS (Address = 80 to 9F Hex)
(for brevity, only channel one is shown; see Table 5-1 for other register address)
(MSB)
C7 C6
SYMBOL POSITION NAME AND DESCRIPTION
C7 RC1.7
C0 RC1.0
RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER
(Address = A4 to A7 Hex)
(MSB)
CH8 CH7
CH16 CH15
CH24 CH23
CH32 CH31
SYMBOL POSITION
CH1 - 32 RCC1.0 – 4.7

12 CLOCK BLOCKING REGISTERS

The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit
Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control RCHBLK and TCHBLK pins
respectively. (The RCHBLK and TCHBLK pins are user programmable outputs that can be forced either
high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD
controller in ISDN–PRI applications.
CH6 CH5
CH14 CH13
CH22 CH21
CH30 CH29
NAME AND DESCRIPTION
0 = do not insert data from the TC register into the transmit data stream
1 = insert data from the TC register into the transmit data stream
C5 C4
MSB of the Code (this bit is sent first to the backplane)
LSB of the Code (this bit is sent last to the backplane)
CH6 CH5
CH14 CH13
CH22 CH21
CH30 CH29
NAME AND DESCRIPTION
Receive Channel Code Insertion Control Bits
0 = do not insert data from the RC1 register into the receive data stream
1 = insert data from the RC1 register into the receive data stream
CH4 CH3
CH12 CH11
CH20 CH19
CH28 CH27
C3 C2
CH4 CH3
CH12 CH11
CH20 CH19
CH28 CH27
54 of 117
DS21354 & DS21554
(LSB)
CH2 CH1
CH10 CH9
CH18 CH17
CH26 CH25
(LSB)
C1 C0
(LSB)
CH2 CH1
CH10 CH9
CH18 CH17
CH26 CH25
TCC1 (A0)
TCC2 (A1)
TCC3 (A2)
TCC4 (A3)
RC1 (80)
RCC1 (A4)
RCC2 (A5)
RCC3 (A6)
RCC4 (A7)