Fas Error Counter; Ds0 Monitoring Function - Dallas Semiconductor DS21354L Manual

EBCR1: E–BIT COUNT REGISTER 1 (Address=04 Hex)
EBCR2: E–BIT COUNT REGISTER 2 (Address=05 Hex)
(MSB)
(note 1) (note 1)
EB7 EB6
SYMBOL POSITION NAME AND DESCRIPTION
EB9 EBCR1.1
EB0 EBCR2.0
NOTE:
The upper six bits of EBCR1 at address 04 are the least significant bits of the 12–bit FAS error counter.

8.4 FAS Error Counter

FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12–bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is
disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS
alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS
word error count in a one second period is 4000, this counter cannot saturate.
FASCR1: FAS ERROR COUNT REGISTER 1 (Address=02 Hex)
FASCR2: FAS ERROR COUNT REGISTER 2 (Address=04 Hex)
(MSB)
FAS11 FAS10
FAS5 FAS4
SYMBOL POSITION NAME AND DESCRIPTION
FAS11 FASCR1.7
FAS0 FASCR2.2
NOTES:
1. The lower two bits of FASCR1 at address 02 are the most significant bits of the 10–bit CRC4 error
counter.
2. The lower two bits of FASCR2 at address 04 are the most significant bits of the 10–bit E–Bit counter.

9 DS0 MONITORING FUNCTION

Each framer in the DS21354/554 has the ability to monitor one DS0 (64kbps) channel in the transmit
direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user
will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4
register. In the receive direction, the RCM0 to RCM4 bits in the CCR5 register need to be properly set.
The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor
(TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive
DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the
decimal decode of the appropriate E1 channel.
(note 1) (note 1)
EB5 EB4
MSB of the 10–Bit E–Bit Error Count
LSB of the 10–Bit E–Bit Error Count
FAS9 FAS8
FAS3 FAS2
MSB of the 12–Bit FAS Error Count
LSB of the 12–Bit FAS Error Count
(note 1) (note 1)
EB3 EB2
FAS7 FAS6
FAS1 FAS0
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DS21354 & DS21554
(LSB)
EB9 EB8
EB1 EB0
(LSB)
(note 2) (note 2)
(note 1) (note 1)
EBCR1
EBCR2
FASCR1
FASCR2