Framer Loopback - Dallas Semiconductor DS21354L Manual

CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)
(MSB)
FLB THDB3
SYMBOL POSITION NAME AND DESCRIPTION
FLB CCR1.7
THDB3 CCR1.6
TG802 CCR1.5
TCRC4 CCR1.4
RSM CCR1.3
RHDB3 CCR1.2
RG802 CCR1.1
RCRC4 CCR1.0

6.2 Framer Loopback

When CCR1.7 is set to a one, the DS21354/554 will enter a Framer LoopBack (FLB) mode. See Figure
3-1 for more details. This loopback is useful in testing and debugging applications. In FLB, the SCT will
loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur:
1. Data will be transmitted as normal at TPOSO and TNEGO.
2. Data input via RPOSI and RNEGI will be ignored.
3. The RCLK output will be replaced with the TCLK input.
TG802 TCRC4
Framer Loopback.
0 = loopback disabled
1 = loopback enabled
Transmit HDB3 Enable.
0 = HDB3 disabled
1 = HDB3 enabled
Transmit G.802 Enable. See Section 19 for details.
0 = do not force TCHBLK high during bit 1 of timeslot 26
1 = force TCHBLK high during bit 1 of timeslot 26
Transmit CRC4 Enable.
0 = CRC4 disabled
1 = CRC4 enabled
Receive Signaling Mode Select.
0 = CAS signaling mode
1 = CCS signaling mode
Receive HDB3 Enable.
0 = HDB3 disabled
1 = HDB3 enabled
Receive G.802 Enable. See Section 19 for details.
0 = do not force RCHBLK high during bit 1 of timeslot 26
1=force RCHBLK high during bit 1 of timeslot 26
Receive CRC4 Enable.
0 = CRC4 disabled
1 = CRC4 enabled
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RSM RHDB3
DS21354 & DS21554
(LSB)
RG802 RCRC4