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21.3 Receive Side AC Characteristics
AC CHARACTERISTICS – RECEIVE SIDE [See Figure 21-8 to Figure 21-10]
PARAMETER
RCLKO Period
RCLKO Pulse Width
RCLKO Pulse Width
RCLKI Period
RCLKI Pulse Width
RSYSCLK Period
RSYSCLK Pulse Width
RSYNC Set Up to RSYSCLK Falling
RSYNC Pulse Width
RPOSI/RNEGI Set Up to RCLKI
Falling
RPOSI/RNEGI Hold From RCLKI
Falling
RSYSCLK/RCLKI Rise and Fall Times
Delay RCLKO to RPOSO, RNEGO
Valid
Delay RCLK to RSER, RDATA, RSIG,
RLINK Valid
Delay RCLK to RCHCLK, RSYNC,
RCHBLK, RFSYNC, RLCLK
Delay RSYSCLK to RSER, RSIG Valid
Delay RSYSCLK to RCHCLK,
RCHBLK, RMSYNC, RSYNC, CO
CI Set Up to RSYSCLK Rising
CI Pulse Width
NOTES:
1. Jitter attenuator enabled in the receive path.
2. Jitter attenuator disabled or enabled in the transmit path.
3. RSYSCLK = 1.544 MHz.
4. RSYSCLK = 2.048 MHz.
5. RSYSCLK = 4.096 MHz
6. RSYSCLK = 8.192 MHz
(0° ° ° ° C to 70° ° ° ° C; V
0° ° ° ° C to 70° ° ° ° C; V
-40° ° ° ° C to +85° ° ° ° C; V
-40° ° ° ° C to +85° ° ° ° C; V
SYMBOL
MIN
t
LP
t
200
LH
t
200
LL
t
150
LH
t
150
LL
t
CP
t
75
CH
t
75
CL
t
100
SP
t
100
SP
t
100
SP
t
100
SP
t
50
SH
t
50
SL
t
20
SU
t
50
PW
t
20
SU
t
20
HD
t
, t
R
F
t
DD
t
D1
t
D2
t
D3
t
D4
t
20
SC
t
50
WC
110 of 117
= 3.3V ± ± ± ± 5% for DS21354L;
DD
= 5.0V ± ± ± ± 5% for DS21554L;
DD
= 3.3V ± ± ± ± 5% for DS21354LN;
DD
= 5.0V ± ± ± ± 5% for DS21554LN)
DD
TYP
MAX
UNITS
488
244
244
244
244
488
648
488
244
122
t
–5
SH
25
50
50
50
50
50
DS21354 & DS21554
NOTES
ns
ns
1
ns
1
ns
2
ns
2
ns
ns
ns
ns
3
ns
4
ns
5
ns
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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