SMART Embedded Computing MVME7100 Programmer's Reference Manual page 82

Programmable Configuration Data
Table A-7
Offset
25 (0x19)
26 (0x1A)
27 (0x1B)
28 (0x1C)
29 (0x1D)
30 (0x1E)
31 (0x1F)
32 (0x20)
33 (0x21)
34 (0x22)
35 (0x23)
36 (0x24)
37 (0x25)
38 (0x26)
39 (0x27)
40 (0x28)
41 (0x29)
80
Variable SPD Contents (continued)
Value Description
50 Minimum Clock Cycle at CLX-2: 0x50 = 5.0 Ns.
Refer to Note
60 Maximum Data Access Time (t AC) from Clock at CLX-2: 0x60 =
0.60ns.
Refer to Note
3C Minimum Row Precharge Time (t RP): 0x3C = 15ns.
Refer to Note
1E Minimum Row Active to Row Active delay (t RRD): 0x1E = 7.5ns.
Refer to Note
3C Minimum RAS to CAS delay (t RCD): 0x3C = 15ns.
Refer to Note
2D Minimum RAS Pulse width (t RAS): 0x2D = 45ns.
Refer to Note
01 Module Bank Density: 0x01 = 1 GB
20 Address and Command Setup Time Before Clock (t lS): 0x20 =
0.20ns.
Refer to Note
28 Address and Command Hold Time After Clock (t lH): 0x28 = 0.28ns.
Refer to Note
10 Data Input Setup Time Before Clock (t DS): 0x10 = 0.1ns.
Refer to Note
18 Data Input Hold Time After Clock (t DH): 0x18 = 0.18ns.
Refer to Note
3C Write Recovery Time (t WR): 0x3C = 15ns
1E Internal Write to Read Command Delay (t WTR): 0x1E = 7.5ns
1E Internal Read to Precharge Command Delay (t RTP): 0x1E = 7.5ns
00 Reserved
06 Extension of Byte 41 and 42
3C Minimum Active to Active/Auto Refresh Time (t RC) 0x3C = 60ns
MVME7100 Single Board Computer Programmer's Reference (6806800E82C)
Programmable Configuration Data
3
.
3
.
3
.
3
.
3
.
3
.
3
.
3
.
3
.
3
.