Table of Contents
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Register Descriptions
The prescaler provides the clock required by each of the four timers. The tick timers require
a 1MHz clock input. The input clock to the prescaler is 25MHz. The default value is set for
$E7 which gives a 1MHz reference clock for a 25MHz input clock source.
3.1.24.2 Control Registers
Table 3-26 Tick Timer Control Registers
REG
BIT
Field
OPER
RESET
ENC
COC
COVF
OVF
ENINT
CINT
INTS
RSVD
40
Tick Timer 1 Control Register - 0xF202 0010 (32 bits)
Tick Timer 2 Control Register - 0xF202 0020 (32 bits)
Tick Timer 3 Control Register - 0xF202 0030 (32 bits)
Tick Timer 4 Control Register - 0xF202 0040 (32 bits)
31
...
11
R
...
R
S
S
V
V
D
D
R/W
0
...
0
Enable counter. When the bit is set the counter increments
When the bit is cleared the counter does not increment.
Clear Counter on Compare. When the bit is set the counter is reset to 0 when
it compares with the compare register.
When the bit is cleared the counter is not reset.
Clear Overflow Bits. The overflow counter is cleared when a 1 is written to this
bit.
Overflow Bits. These bits are the output of the overflow counter. The overflow
counter is incremented each time the tick timer sends an interrupt to the local
bus interrupter. The overflow counter can be cleared by writing a 1 to the
COVF bit.
Enable Interrupt. When the bit is set the interrupt is enabled.
When the bit is cleared the interrupt is not enabled.
Clear Interrupt.
Interrupt Status.
Reserved for future implementation.
MVME7100 Single Board Computer Programmer's Reference (6806800E82C)
10
9
8
7
I
C
E
OVF
N
I
N
T
N
I
S
T
N
T
0
0
0
0
Register Descriptions
6
5
4
3
2
R
C
S
O
V
V
D
F
0
0
0
0
0
1
0
C
E
O
N
C
C
0
0
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