Interrupt Register 1 - SMART Embedded Computing MVME7100 Programmer's Reference Manual

Register Descriptions
Figure 3-1 Boot Flash Bank
3.1.5

Interrupt Register 1

The MVME7100 provides an Interrupt Register that may be read by the system software to
determine which of the Ethernet PHYs originated their combined (OR'd) interrupt.
Table 3-6
REG
BIT
Field
OPER
RESET
PHY1
PHY2
PHY3
PHY4
RSVD
28
Interrupt Register 1
Interrupt Register 1 - 0xF200 0004
7 6 5
RSVD RSVD RSVD
R
0 0 0
TSEC1 PHY Interrupt. If cleared, the TSEC1 interrupt is not asserted. If set,
the TSEC1 interrupt is asserted.
TSEC2 PHY Interrupt. If cleared, the TSEC2 interrupt is not asserted. If set,
the TSEC2 interrupt is asserted.
TSEC3 Interrupt. If cleared, the TSEC3 interrupt is not asserted. If set, the
TSEC4 interrupt is asserted.
TSEC4 Interrupt. If cleared, the TSEC4 interrupt is not asserted. If set, the
FEC interrupt is asserted.
Reserved for future implementation.
MVME7100 Single Board Computer Programmer's Reference (6806800E82C)
4 3 2
RSVD PHY4 PHY3
0 0 0
Register Descriptions
1 0
PHY2 PHY1
0 0