3.1.16 Watch Dog Timer Load Register; 3.1.17 Watch Dog Control Register; Table 3-17 Watch Dog Timer Load Register - SMART Embedded Computing MVME7100 Programmer's Reference Manual

3.1.16 Watch Dog Timer Load Register

The MVME7100 provides a watch dog timer load register.

Table 3-17 Watch dog timer Load Register

REG
BIT
Field
OPER
RESET
LOAD

3.1.17 Watch Dog Control Register

The MVME7100 provides a watch dog timer control register.
Table 3-18 Watch Dog Timer Control Register
REG
BIT
Field
OPER
RESET
SYSRST
EN
RSVD
MVME7100 Single Board Computer Programmer's Reference (6806800E82C)
Watch Dog Timer Control Register - 0xF200 0020
7 6
Load
R/W
0 0
Counter Load. When the pattern 0xDB is written the watch dog counter will be
loaded with the count value.
Watch Dog Timer Control Register - 0xF200 0024
7 6 5
EN SYS RSVD
RST
R/W R
0 0 0
System Reset. If cleared a board-level reset is generated when a time-out
occurs. If set, a VMEbus SYSRST is generated when a time-out occurs. If
MVME7100 is SYSCON then a local reset will also result in a VMEbus
SYSRST.
Enable. If cleared the watch dog timer is disabled. If set the watch dog timer
is enabled.
Reserved for future implementation.
5 4 3
0 0 0
4 3
RSVD RSVD
0 0
Register Descriptions
2 1
0 0
2 1 0
RSVD RSVD RSVD
0 0 0
0
0
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