SMART Embedded Computing MVME7100 Programmer's Reference Manual page 81

Table A-7
Offset
09 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
16 (0x10)
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
21 (0x15)
22 (0x16)
23 (0x17)
24 (0x18)
MVME7100 Single Board Computer Programmer's Reference (6806800E82C)
Variable SPD Contents (continued)
Value Description
30 SDRAM Cycle time at Maximum Supported CAS Latency (CL),
CL=X: 0x30 = 3.0ns.
Refer to Note
45 SDRAM Access time from Clock at Maximum Supported CAS
Latency (CL), CL=X: 0x45 = 0.45ns.
Refer to Note
02 DIMM configuration type (Non-parity, Parity or ECC): 0x02 = ECC
82 Refresh Rate/Type: 0x82 = 7.8us.
Refer to Notes
08 Primary SDRAM Width: 0x08 = 8 bits
08 Error Checking SDRAM Width: 0x08 = 8 bits
00 Reserved
0C SDRAM Device Attributes - Burst Lengths Supported: 0x0C = 4, and
8 burst lengths
08 SDRAM Device Attributes - Number of Banks on SDRAM Device:
0x08 = 8 banks.
Refer to Note
38 SDRAM Device Attributes - CAS Latency: 0x38 = CAS latency 3, 4,
and 5.
Refer to Note
01 DIMM Mechanical Characteristics
02 DIMM Type Information
00 SDRAM Module Attributes
07 SDRAM Device Attributes - General: 0x00 = PASR, ODT and Weak
Driver.
Refer to Note
3D Minimum Clock Cycle at CLX-1: 0x3D = 3.75ns.
Refer to Note
50 Maximum Data Access Time (t AC) from Clock at CLX-1: 0x50 =
0.50ns.
Refer to Note
Programmable Configuration Data
3
.
3
.
3 4
and .
3
.
3
.
3
.
3
.
3
.
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