SMART Embedded Computing MVME7100 Programmer's Reference Manual page 50

Programming Details
Table 4-1
MC864xD
Signal
TSECn_TX
D5
TSECn_TX
D[6:7]
TSEC1_TX
D[2:4]
LWE1
D1_MSRCI
D[0]
D1_MSRCI
D[1]
48
MC864xD POR Configuration Settings (continued)
Default
Select
POR
Option
Settings
0
Resistors
(pull-
downs)
Resistor 10
Processor
111
Default
Control
1
PLD
1
No
(processor
Connect
default)
1
No
(processor
Connect
default)
MVME7100 Single Board Computer Programmer's Reference (6806800E82C)
Description State of Bit vs Function1
0
eTSEC Width
Configuration
1
00
01
eTSECn
Protocol
Configuration
10
11
RapidIO
Device ID
Device ID used for serial RapidIO hosts.
Serial 0
RapidIO
1
System Size
0
Memory
Debug
Configuration
1
0
DDR Debug
Configuration
1
Programming Details
Ethernet interface operates in
reduced mode, RTBI or RGMII.
Ethernet interface operates in
standard TBI or GMII modes.
eTSECn controller operates
using FIFO.
eTSECn controller operates
using MII(RMII).
eTSECn controller operates
using GMII(RGMII)
eTSECn controller operates
using TBI
Up to 65,536 devices
Up to 256 devices
Debug information from LBC is
driven on the D1_MSRCIDn and
D1_MDVAL signals
Debug information from DDR
SDRAM controller is driven on
the D1_MSRCID and
D1_MDVAL signals
DDR debug information is driven
on the ECC pins instead of the
normal ECC I/O.
DDR debug information is not
driven on the ECC pins.