SMART Embedded Computing MVME7100 Programmer's Reference Manual page 76

Programmable Configuration Data
Table A-6
Value
17 (0x11)
18 (0x12)
19 (0x13)
20 (0x14)
21 (0x15)
22 (0x16)
23 (0x17)
24 (0x18)
25 (0x19)
26 (0x1A)
27 (0x1B)
28 (0x1C)
29 (0x1D)
30 (0x1E)
31 (0x1F)
74
Static SPD Contents (continued)
Offset Description
04 SDRAM Device Attributes - Number of Banks on SDRAM Device:
0x04 = 4 banks.
Refer to Note
38 SDRAM Device Attributes - CAS Latency: 0x38 = CAS latency 3, 4,
and 5.
Refer to Note
01 DIMM Mechanical Characteristics
02 DIMM Type Information
00 SDRAM Module Attributes
07 SDRAM Device Attributes - General: 0x00 = PASR, ODT and Weak
Driver.
Refer to Note
3D Minimum Clock Cycle at CLX-1: 0x3D = 3.75ns.
Refer to Note
50 Maximum Data Access Time (t AC) from Clock at CLX-1: 0x50 =
0.50ns.
Refer to Note
50 Minimum Clock Cycle at CLX-2: 0x50 = 5.0 Ns.
Refer to Note
60 Maximum Data Access Time (t AC) from Clock at CLX-2: 0x60 =
0.60ns.
Refer to Note
3C Minimum Row Precharge Time (t RP): 0x3C = 15ns.
Refer to Note
1E Minimum Row Active to Row Active delay (t RRD): 0x1E = 7.5ns.
Refer to Note
3C Minimum RAS to CAS delay (t RCD): 0x3C = 15ns.
Refer to Note
2D Minimum RAS Pulse width (t RAS): 0x2D = 45ns.
Refer to Note
80 Module Bank Density: 0x80 = 512 MB
MVME7100 Single Board Computer Programmer's Reference (6806800E82C)
Programmable Configuration Data
3
.
3
.
3
.
3
.
3
.
3
.
3
.
3
.
3
.
3
.
3
.