PMC133
MASTER WP
SW8
3.1.2
System Control Register
The MVME7100 has a System Control Register that provides general board control bits.
Table 3-3
REG
BIT
Field
OPER
RESET
EEPROM_WP EEPROM Write Protect. This bit is to provide protection against
BRD_RST
RSVD
MVME7100 Single Board Computer Programmer's Reference (6806800E82C)
PMC133. This bit reflects the current state of the PMC 133MHz
switch. A Cleared condition indicates the switch is off. A set
condition indicates the switch is on. When this switch is on, the
maximum PMC clock frequency is 133MHz. When this switch is
off, the maximum PMC clock frequency is 100MHz.
MASTER WP. This bit reflects the current state of the MASTER
WP switch. A cleared condition indicates the switch is off. A set
condition indicates the switch is on. When this switch is on, the
NOR FLASH, NAND FLASH, MRAM and I
protected. When this switch is off, NOR FLASH, NAND FLASH,
MRAM and I
Other switches and control bits may write protect individual
devices.
SW8. This bit reflects the current state of SW8. A cleared
condition indicates the switch is off. A set condition indicates the
switch is on.
System Control Register
System Control Register - 0xF200 0001
7
6
5
BRD_RST
R/W
0
0
0
inadvertent writes to the on-board EEPROM devices. Clearing this bit
will enable writes to the EEPROM devices. Setting this bit write protects
the devices. The devices are write protected following a reset.
Board Reset. These bits are used to force a hard reset of the board. If a
pattern is written in bits 5-7 where bit 7 is set, bit 6 is cleared, and bit 5
is set (101), a hard reset is generated. Any other pattern written in bits
5-7, does not generate a hard reset. These bits are cleared automatically
when the board reset has been completed. These bits are always
cleared during a read.
Reserved for future implementation.
2
C EPROMs are not write protected by this function.
4
3
2
RSVD
RSVD
RSVD
R
R
R
0
0
0
Register Descriptions
2
C EPROMs are write
1
0
EEPROM_
RSVD
WP
R/W
R
1
0
25
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