Kb/Ms/Lpc/Gpio/Smbus Combination Pin Header; Figure 12: Kb/Ms/Lpc/Gpio/ Smbus Combination Pin Header Diagram; Table 11: Kb/Ms/Lpc/Gpio/Smbus Combination Pin Header Pinouts - VIA Technologies EPIA-P910 User Manual

2.2.4. KB/MS/LPC/GPIO/SMBus Combination Pin Header

The VIA EPIA-P910 includes one KB, MS, LPC, GPIO, and SMBus combination pin header block labeled as
"CN1". The combination pin header is for connecting KB, MS, LPC, GPIO, and SMBus devices. The pinouts
of the pin header are shown below.

Figure 12: KB/MS/LPC/GPIO/ SMBus combination pin header diagram

Pin
1 LAD3
3 LAD2
5 LAD1
7 -LFRAME
9 LAD0
11 -PCIRST
13 SMBDT_+3.3V
15 +3.3V
17 -LID/GPI7
19 -THRM/GPI9
21 -EXTSMI/GPI5
23 -BATLOW/GPI4
25 GND
27 KBDT
29 MSDT

Table 11: KB/MS/LPC/GPIO/SMBus combination pin header pinouts

Signal Pin
2 GND
4 SIO_CLK1
6 PCICLK3
8 -LDRQ0
10 SERIRQ
12 GND
14 SMBCK_+3.3V
16 +5V
18 -INTB/GPIO8
20 -INTC/GPIO9
22 GPIO12/GPIO12
24 GPIO32/GPIO32
26 +5VSUS
28 KBCK
30 MSCK
VIA EPIA-P910 User Manual
Signal
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