Dram Configuration; Dram Clock; Vga Share Memory (Frame Buffer); Figure 43: Illustration Of Dram Configuration Screen - VIA Technologies EPIA-P910 User Manual

VIA EPIA-P910 User Manual

6.6.1. DRAM Configuration

The DRAM Configuration screen has two features for controlling the system DRAM. All other DRAM
features are automated and cannot be accessed.

Figure 43: Illustration of DRAM Configuration screen

6.6.1.1. DRAM Clock

The DRAM Clock option enables the user to determine how the BIOS handles the memory clock
frequency. The memory clock can either be dynamic or static. This feature has eleven options.
By SPD
By SPD option enables the BIOS to select a compatible clock frequency for the installed memory.
400 MHz
The 400 MHz option forces the BIOS to be fixed at 800 MHz for DDR3 memory modules.
533 MHz
The 533 MHz option forces the BIOS to be fixed at 1066 MHz for DDR3 memory modules.
566 MHz
The 566 MHz option forces the BIOS to be fixed at 1132 MHz for DDR3 memory modules.
600 MHz
The 600 MHz option forces the BIOS to be fixed at 1200 MHz for DDR3 memory modules.
633 MHz
The 633 MHz option forces the BIOS to be fixed at 1266 MHz for DDR3 memory modules.
667 MHz
The 667 MHz option forces the BIOS to be fixed at 1334 MHz for DDR3 memory modules.

6.6.1.2. VGA Share Memory (Frame Buffer)

The VGA Share Memory feature enables the user to choose the amount of the system memory to reserve
for use by the integrated graphics controller. The selections of memory amount that can be reserved are
256MB and 512MB.
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