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Contents
of
Timer 2
Timer Count = Reload Value
Compare
Output
(P1.x/CCx)
Figure 7-37
Function of Compare Mode 0
Modulation Range in Compare Mode 0
Generally it can be said that for every PWM generation in compare mode 0 with n-bit wide compare
n
registers there are 2
cycle) as the first setting, the maximum possible duty cycle then would be
This means that a variation of the duty cycle from 0% to real 100% can never be reached if the
compare register and timer register have the same length. There is always a spike which is as long
as the timer clock period.
This "spike" may either appear when the compare register is set to the reload value (limiting the
lower end of the modulation range) or it may occur at the end of a timer period. In a timer 2/CCx
register configuration in compare mode 0 this spike is divided into two halves: one at the beginning
when the contents of the compare register is equal to the reload value of the timer; the other half
when the compare register is equal to the maximum value of the timer register (here: 0FFFF H ).
Please refer to figure 7-38 where the maximum and minimum duty cycle of a compare output signal
is illustrated. Timer 2 is incremented with the machine clock (
frequency, these spikes are both approx. 500 ns long.
Semiconductor Group
Interrupt can be generated
on overflow
different settings for the duty cycle. Starting with a constant low level (0% duty
(1 – 1/2
On-Chip Peripheral Components
*
Interrupt can be generated
on compare-match
n
) x 100%
f
/12), thus at 12-MHz operational
OSC
90
Timer Count = FFFF
H
Timer Count =
Compare Value
MCT01906
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