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On-Chip Peripheral Components
7.1.4
Port Handling
7.1.4.1 Port Timing
When executing an instruction that changes the value of a port latch, the new value arrives at the
latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by
their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the
value it noticed during the previous phase 1). Consequently, the new value in the port latch will not
appear at the output pin until the next phase 1, which will be at S1P1 of the next machine cycle.
When an instruction reads a value from a port pin (e.g. MOV A, P1) the port pin is actually sampled
in state 5 phase 1 or phase 2 depending on port and alternate functions. Figure 7-6 illustrates this
port timing. lt must be noted that this mechanism of sampling once per machine cycle is also used
if a port pin is to detect an "edge", e.g. when used as counter input. In this case an "edge" is
detected when the sampled value differs from the value that was sampled the cycle before.
Therefore, there must be met certain requirements on the pulse length of signals in order to avoid
signal "edges" not being detected. The minimum time period of high and low level is one machine
cycle, which guarantees that this logic level is noticed by the port at least once.
*
Figure 7-6
Port Timing
Semiconductor Group
44
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