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8
Interrupt System
The SAB 80C515/80C535 provides 12 interrupt sources with four priority levels.
Five interrupts can be generated by the on-chip peripherals (i.e. timer 0, timer 1, timer 2, compare
timer, serial interface and A/D converter), and seven interrupts may be triggered externally (see
figure 8.1).
8.1
Interrupt Structure
A common mechanism is used to generate the various interrupts, each source having its own
request flag(s) located in a special function register (e.g. TCON, IRCON, SCON). Provided that the
peripheral or external source meets the condition for an interrupt, the dedicated request flag is set,
whether an interrupt is enabled or not. For example, each timer 0 overflow sets the corresponding
request flag TF0. lf it is already set, it retains a one (1). But the interrupt is not necessarily serviced.
Now each interrupt requested by the corresponding flag can individually be enabled or disabled by
the enable bits in SFR's IEN0, IEN1 (see figure 8-2, 8-3). This determines whether the interrupt will
actually be performed. In addition, there is a global enable bit for all interrupts which, when cleared,
disables all interrupts independent of their individual enable bits.
Semiconductor Group
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112
Interrupt System
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