Page 1 Microcomputer Components SAB 80515/SAB 80C515 8-Bit Single-Chip Microcontroller Family User's Manual 08.95...
Page 2 The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).
Page 3 Contents Contents Page Introduction ..........6 Fundamental Structure .
Page 4 Contents Contents Page 7.1.4.2 Port Loading and Interfacing ........45 7.1.4.3 Read-Modify-Write Feature of Ports 0 through 5 .
Page 5 Contents Contents Page Oscillator and Clock Circuit ........107 7.8.1 Crystal Oscillator Mode .
Page 6 Introduction Introduction The SAB 80C515/80C535 is a new, powerful member of the Siemens SAB 8051 family of 8-bit microcontrollers. lt is designed in Siemens ACMOS technology and is functionally compatible with the SAB 80515/80535 devices designed in MYMOS technology. 1) 2)
Page 7 Introduction The SAB 80(C)515 features are: – 8 Kbyte on-chip program memory – 256 byte on-chip RAM – Six 8-bit parallel I/O ports – One input port for digital input – Full-duplex serial port, 4 modes of operation, fixed or variabie baud rates –...
Page 8 Introduction Figure 1-1 shows the logic symbol, figure 1-2 the block diagram of the SAB 80(C)515: Figure 1-1 Logic Symbol Semiconductor Group...
Page 9 Introduction Figure 1-2 Block Diagram Semiconductor Group...
Page 10 Fundamental Structure Fundamental Structure The SAB 80(C)515/80(C)535 is a totally 8051-compatible microcontroller while its peripheral performance has been increased significantly. Some of the various peripherals have been added to support the 8-bit core in case of stringent embedded control requirements without loosing compatibility to the 8051 architecture. Furthermore, the SAB 80(C)515/80(C)535 contains e.
Page 11 Fundamental Structure Central Processing Unit The CPU is designed to operate on bits and bytes. The instructions, which consist of up to 3 bytes, are performed in one, two or four machine cycles. One machine cycle requires twelve oscillator cycles. The instruction set has extensive facilities for data transfer, logic and arithmetic instructions. The Boolean processor has its own full-featured and bit-based instructions within the instruction set.
Page 12 Fundamental Structure Figure 2-1 Detailed Block Diagram Semiconductor Group...
Page 13 Fundamental Structure Differences between MYMOS (SAB 80515/80535) and ACMOS (SAB 80C515/80C535) Versions There are some differences between MYMOS and ACMOS versions concerning: – Power Saving Modes – Special Function Register PCON – Port Driver Circuitry – A/D Converter Input Ports –...
Page 14 Fundamental Structure 2.1.3 Port Driver Circuitries The port structures of the MYMOS and ACMOS versions are functionally compatible. For low power consumption the pullup arrangement is realized differently in both versions. Chapters 7.1.1.1, 7.1.1.2, 7.1.1.3 are dealing with the port structures in detail. 2.1.4 The A/D Converter Input Ports The analog input ports (AN0 to AN7) of the SAB 80515/80535 can only be used as analog inputs...
Page 15 Fundamental Structure 2.1.5 A/D Converter Timings See the corresponding data sheets for the specification of (load time), (sample time), (conversion time). 2.1.6 The Oscillator and Clock Circuits There is no difference between the MYMOS and ACMOS versions if they are driven from a crystal or a ceramic resonator.
Page 16 Central Processing Unit Central Processing Unit General Description The CPU (Central Processing Unit) of the SAB 80(C)515 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU.
Page 17 Central Processing Unit CPU Timing A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active.
Page 18 Central Processing Unit Figure 3-1 Fetch/Execute Sequence Semiconductor Group...
Page 19 Memory Organization Memory Organization The SAB 80(C)515 CPU manipulates operands in the following four address spaces: – up to 64 Kbyte of program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory –...
Page 20 Memory Organization Address Space Locations Addressing Mode Lower 128 bytes of RAM 00 H to 7F H direct/indirect Upper 128 bytes of RAM 80 H to 0FF H indirect Special function registers 80 H to 0FF H direct For details about the addressing modes see chapter 9.1. Figure 4-1 Program Memory Address Space The lower 128 bytes of the internal RAM are again grouped in three address spaces...
Page 21 Memory Organization Using the Stack Pointer (SP) - a special function register described in section 4.4 - the stack can be located anywhere in the whole internal data memory address space. The stack depth is limited only by the internal RAM available (256 byte maximum). However, the user has to take care that the stack is not overwritten by other data, and vice versa.
Page 22 Memory Organization Figure 4-3 Mapping of the Lower Portion of the Internal Data Memory Semiconductor Group...
Page 23 Memory Organization General Purpose Register The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose register (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, PSW.3 and PSW.4, select the active register bank (see description of the PSW).
Page 24 Memory Organization Table 4-1 Special Function Registers Symbol Name Address Port 0 80 H Stack pointer 81 H Data pointer, low byte 82 H Data pointer, high byte 83 H PCON Power control register 87 H 88 H TCON Timer control register TMOD Timer mode register 89 H...
Page 25 Memory Organization The following paragraphs give a general overview of the special function register and refer to sections where a more detailed description can be found. Accumulator, SFR Address 0E0 H ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A.
Page 26 Memory Organization Datapointer, SFR Address 082 H and 083 H The 16-bit Datapointer (DPTR) register is a concatenation of registers DPH (data pointer’s high order byte) and DPL (data pointer’s low order byte). The data pointer is used in register-indirect addressing to move program memory constants and external data memory variables, as well as to branch within the 64 Kbyte program memory address space.
Page 27 External Bus Interface External Bus Interface The SAB 80(C)515 allows for external memory expansion. To accomplish this, the external bus interface common to most 8051-based controllers is employed. Accessing External Memory lt is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively.
Page 28 External Bus Interface Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD and information on port 0 and port 2, is illustrated in figure 5-1 a) and b). Data memory: in a write cycle, the data byte to be written appears on port 0 just before WR is activated, and remains there until after WR is deactivated.
Page 29 External Bus Interface PSEN, Program Store Enable The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external program memory, PSEN is activated twice every cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction.
Page 30 External Bus Interface Figure 5-1 a) and b) External Program Memory Execution Semiconductor Group...
Page 31 System Reset System Reset Hardware Reset and Power-Up Reset 6.1.1 Reset Function and Circuitries The hardware reset function incorporated in the SAB 80(C)515 allows for an easy automatic start- up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device.
Page 32 System Reset Figure 6-1 a) - c) Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000 H . The default values of the special function registers (SFR) during and after reset are listed in table 6-1.
Page 33 System Reset Table 6-1 Register Contents after Reset Register Contents Register Contents P0 - P5 0FF H 07 H DPTR 0000 H PCON 000X 0000B TCON 00 H TMOD 00 H TL0, TH0 00 H TL1, TH1 00 H TL2, TH2 00 H SCON 00 H...
Page 34 System Reset 6.1.2 Hardware Reset Timing This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (low level at pin 10) the internal reset procedure is started.
Page 35 On-Chip Peripheral Components On-Chip Peripheral Components This chapter gives detailed information about all on-chip peripherals of the SAB 80(C)515 except for the integrated interrupt controller, which is described separately in chapter 8. Sections 7.1 and 7.2 are associated with the general parallel and serial I/O facilities while the remaining sections describe the miscellaneous functions such as the timers, serial interface, A/D converter, power saving modes, watchdog timer, oscillator and clock circuitries, and system clock output.
Page 36 On-Chip Peripheral Components lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications ). Since P6 is not a bit-addressable register, all input lines of P6 are read at the same time by byte instructions.
Page 37 On-Chip Peripheral Components Port 1 through 5 output drivers have internal pullup FET’s (see figure 7-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit must contain a one (1) (that means for figure 7-2: Q = 0), which turns off the output driver FET n1.
Page 38 On-Chip Peripheral Components Figure 7-3 Output Driver Circuits of Ports 1 through 5 Semiconductor Group...
Page 39 On-Chip Peripheral Components 7.1.1.2 MYMOS Port Driver Circuitry The output driver circuitry of the MYMOS version (figure 7-3) consists of two pullup FETs (pullup arrangements) and one pulldown FET: – The transistor n1 is a very strong pullup transistor which is only activated for two oscillator periods, if a 0-to-1 transition is executed by this port bit.
Page 40 On-Chip Peripheral Components If a pin is used as input and a low level is applied, it will be in IL state, if a high level is applied, it will switch to IH state. If the latch is loaded with "0", the pin will be in OL state. If the latch holds a "0"...
Page 41 On-Chip Peripheral Components 7.1.2 Port 0 and Port 2 Used as Address/Data Bus As shown in figures 7-4 a) and 7-4 b), the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally.
Page 42 On-Chip Peripheral Components 7.1.3 Alternate Functions Several pins of ports 1 and 3 are multifunctional. They are port pins and also serve to implement special features as listed in table 7-1. Table 7-1 Port Alternate Function P1.0 INT3/CC0 Ext. interrupt 3 input, compare 0 output, capture 0 input P1.1 INT4/CC1 Ext.
Page 43 On-Chip Peripheral Components Figure 7-5 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open. Thus, to use the alternate input or output functions, the corresponding bit latch in the port SFR has to contain a one (1);...
Page 44 On-Chip Peripheral Components 7.1.4 Port Handling 7.1.4.1 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1).
Page 45 On-Chip Peripheral Components 7.1.4.2 Port Loading and Interfacing The output buffers of ports 1 through 5 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can belooked up in the DC characteristics in the Data Sheet of the SAB 80(C)515.
Page 46 On-Chip Peripheral Components Table 7-2 Read-Modify-Write Instructions Instruction Function Logic AND; e.g. ANL P1, A Logic OR; e.g. ORL P2, A Logic exclusive OR; e.g. XRL P3, A Jump if bit is set and clear bit; e.g. JBC P1.1, LABEL Complement bit;...
Page 47 On-Chip Peripheral Components Serial Interfaces The serial port of the SAB 80(C)515S enables communication between microcontrollers or between the microcontroller and peripheral devices. The serial port is full-duplex, meaning it can transmit and receive simultaneously. It is also receive buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still has not been read by the time reception of the second byte is complete, the last received byte will be lost).
Page 48 On-Chip Peripheral Components In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in mode 0 by the condition RI = 0 and REN = 1. Reception is initiated in the other modes by the incoming start bit if REN = 1. The serial interfaces also provide interrupt requests when a transmission or a reception of a frame has completed.
Page 49 On-Chip Peripheral Components The control and status bits of the serial channel in special function register SCON are illustrated in figure 7-8. Figure 7-7 shows the special function register SBUF which is the data register for receive and transmit. The following table summarizes the operating modes of the serial interface. Table 7-3 Serial Interface, Mode Selection Mode...
Page 50 On-Chip Peripheral Components 7.2.2 Multiprocessor Communication Feature Modes 2 and 3 of the serial interface 0 have a special provision for multi-processor communication. In these modes, 9 data bits are received. The 9th bit goes into RB8. Then a stop bit follows. The port can be programmed such that when the stop bit is received, the serial port 0 interrupt will be activated (i.e.
Page 51 On-Chip Peripheral Components Mode 0 The baud rate in mode 0 is fixed: oscillator frequency Mode 0 baud rate = Mode 2 The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON (see figure 7-9).
Page 52 On-Chip Peripheral Components Figure 7-10 Special Function Register ADCON (Address 0D8 H ) 0DF H 0DE H 0DD H 0DC H 0DB H 0DA H 0D9 H 0D8 H 0D8 H ADEX ADCON These bits are not used in controlling serial interface. Function Baud rate enable.
Page 53 On-Chip Peripheral Components Table 7-4 Timer 1 Generated Commonly Used Baud Rates Baud Rate (MHz) SMOD Timer 1 Mode Reload Value Mode 1, 3: 62.5 Kbaud 12.0 FF H 19.5 Kbaud 11.059 FD H 9.6 Kbaud 11.059 FD H FA H 4.8 Kbaud 11.059 F4 H...
Page 54 On-Chip Peripheral Components Table 7-5 Baud Rates of Serial Interface 0 Baud Rate Derived Interface Baud Rate from Mode Timer 1 in mode 1 1, 3 SMOD x (timer 1 overflow rate) Timer 1 in mode 2 1, 3 SMOD 12 x (256 –...
Page 55 On-Chip Peripheral Components SEND enables the output of the shift register to the alternate output function line P3.0, and also enables SHIFT CLOCK to the alternate output function line P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every machine cycle, and high during S6, S1, and S2, while the interface is transmitting.
Page 56 On-Chip Peripheral Components Transmission is initiated by any instruction that uses SBUF as a destination register. The "write-to- SBUF" signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX control block that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next roll-over in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the "write-to-SBUF"...
Page 57 On-Chip Peripheral Components 7.2.4.3 Mode 2, 9-Bit UART Mode 2 is functionally identical to mode 3 (see below). The only exception is, that in mode 2 the baud rate can be programmed to two fixed quantities: either 1/32 or 1/64 of the oscillator frequency. In mode 3 the baud rate clock is generated by timer 1, which is incremented by a rate of /12 or by the internal baud rate generator.
Page 58 On-Chip Peripheral Components At the 7th, 8th and 9th counter state of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. lf the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition.
Page 59 On-Chip Peripheral Components Figure 7-16 a) Functional Diagram - Serial Interface, Mode 0 Semiconductor Group...
Page 60 On-Chip Peripheral Components Figure 7-16 b) Timing Diagram - Serial Interface, Mode 0 Semiconductor Group...
Page 61 On-Chip Peripheral Components Figure 7-17 a) Functional Diagram - Serial Interface, Mode 1 Semiconductor Group...
Page 62 On-Chip Peripheral Components Figure 7-17 b) Timing Diagram - Serial Interface, Mode 1 Semiconductor Group...
Page 63 On-Chip Peripheral Components Figure 7-18 a) Functional Diagram - Serial Interface, Modes 2 and 3 Semiconductor Group...
Page 64 On-Chip Peripheral Components Figure 7-18 b) Timing Diagram - Serial Interface, Modes 2 and 3 Semiconductor Group...
Page 65 On-Chip Peripheral Components Timer 0 and Timer 1 The SAB 80(C)515 three general purpose 16-bit timer/counters: timer 0, timer 1, timer 2 and the compare timer (timer 2 is discussed separately in section 7.5). Timer/counter 0 and 1 are fully compatible with timer/counters 0 and 1 of the SAB 80(C)51 and can be used in the same operating modes.
Page 66 On-Chip Peripheral Components Figure 7-19 Special Function Register TCON (Address 88 H ) 8F H 8E H 8D H 8C H 8B H 8A H 89 H 88 H 88 H TCON These bits are not used in controlling timer/counter 0 and 1. Function Timer 0 run control bit.
Page 67 On-Chip Peripheral Components Figure 7-20 Special Function Register TMOD (Address 89 H ) 89 H GATE GATE TMOD Timer 1 Timer 0 Timer/counter 0/1 mode control register. Symbol Gate Gating control. When set, timer/counter "x" is enabled only while "INTx" pin is high and "TRx"...
Page 68 On-Chip Peripheral Components 7.3.1 Mode 0 Putting either timer/counter into mode 0 configures it as an 8-bit timer/counter with a divide-by-32 prescaler. Figure 7-21 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0.
Page 69 On-Chip Peripheral Components 7.3.2 Mode 1 Mode 1 is the same as mode 0, except that the timer register is run with all 16 bits. Mode 1 is shown in figure 7-22. Figure 7-22 Timer/Counter 0, Mode 1: 16-Bit Timer/Counter The same applies to timer/counter 1 Semiconductor Group...
Page 70 On-Chip Peripheral Components 7.3.3 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in figure 7-23. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software.
Page 71 On-Chip Peripheral Components 7.3.4 Mode 3 Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1 = 0. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters.
Page 72 On-Chip Peripheral Components A/D Converter The SAB 80(C)515 provides an A/D converter with the following features: – Eight multiplexed input channels – The possibility of using the analog input channels (port 6) as digital inputs (ACMOS version only). – Programmable internal reference voltages (16 steps each) via resistor array –...
Page 73 On-Chip Peripheral Components Figure 7-25 A/D Converter Block Diagram Semiconductor Group...
Page 74 On-Chip Peripheral Components 7.4.1 Function and Control 7.4.1.1 lnitialization and Input Channel Selection Special function register ADCON which is illustrated in figure 7-26 is used to set the operating modes, to check the status, and to select one of eight analog input channels. Figure 7-26 Special Function Register ADCON (Address 0D8 H ) 0DF H...
Page 75 On-Chip Peripheral Components Table 7-6 Selection of the Analog Input Channels Selected Channel MYMOS ACMOS Analog input 0 P6.0 Analog input 1 P6.1 Analog input 2 P6.2 Analog input 3 P6.3 Analog input 4 P6.4 Analog input 5 P6.5 Analog input 6 P6.6 Analog input 7 P6.7...
Page 76 On-Chip Peripheral Components 7.4.2 Reference Voltages The SAB 80(C)515 has two pins to which a reference voltage range for the on-chip A/D converter is applied (pin for the upper voltage and pin for the lower voltage). In contrast to AREF AGND conventional A/D converters it is now possible to use not only these externally applied reference voltages for the conversion but also internally generated reference voltages which are derived from...
Page 77 On-Chip Peripheral Components If DAPR (.3-.0) or DAPR (.7-.4) = 0, the internal reference voltages correspond to the external reference voltages , respectively. AGND AREF < V > , the conversion result is 0FF H , if , the conversion result is 00 H AINPUT IntAREF AINPUT...
Page 78 On-Chip Peripheral Components Table 7-7 Adjustable Internal Reference Voltages Step DAPR (.3-.0) IntAGND IntAREF DAPR (.7-.4) 0000 0001 0.3125 – 0010 0.625 – 0011 0.9375 – 0100 1.25 1.25 0101 1.5625 1.5625 0110 1.875 1.875 0111 2.1875 2.1875 1000 1001 2.8125 2.8125 1010...
Page 79 On-Chip Peripheral Components Figure 7-30 Adjusting the Internal Reference Voltages within Range of the External Analog Input Voltages Figure 7-31 Increasing the Resolution by a Second Conversion Semiconductor Group...
Page 80 On-Chip Peripheral Components The external reference voltage supply need only be applied when the A/D converter is used, otherwise the pins may be left unconnected. The reference voltage supply has to AREF AGND meet some requirements concerning the level of and the output impedance of the AGND AREF...
Page 81 On-Chip Peripheral Components Conversion time ( The conversion time includes the sample and load time. Thus, is the total time required for one conversion. After the load time and sample time have elapsed, the conversion itself is performed during the rest of .
Page 82 On-Chip Peripheral Components Timer 2 with Additional Compare/Capture/Reload The timer 2 with additional compare/capture/reload features is one of the most powerful peripheral units of the SAB 80(C)515. lt is used for all kinds of digital signal generation and event capturing like pulse generation, pulse width modulation, pulse width measuring etc.
Page 83 On-Chip Peripheral Components Figure 7-33 a) Timer 2 Block Diagram Semiconductor Group...
Page 84 On-Chip Peripheral Components Figure 7-33 b) Timer 2 in Reload Mode Table 7-8 Alternate Port Functions of Timer 2 Pin Symbol Input (I) Function Output (O) P1.7/T2 External count or gate input to timer 2 P1.5/T2EX External reload trigger input P1.3/INT6/CC3 Comp.
Page 85 On-Chip Peripheral Components Table 7-9 Additional Special Function Registers of Timer 2 Symbol Description Address CCEN Comp./capture enable reg. 0C1 H CCH1 Comp./capture reg. 1, high byte 0C3 H CCH2 Comp./capture reg. 2, high byte 0C5 H Comp./capture reg. 3, high byte 0C7 H CCH3 Comp./capture reg.
Page 86 On-Chip Peripheral Components Event Counter Mode In the counter function, the timer 2 is incremented in response to a 1-to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is sampled every machine cycle. When the sampled inputs show a high in one cycle and a low in the next cycle, the count is incremented.
Page 87 On-Chip Peripheral Components Figure 7-34 Special Function Register T2CON 0CF H 0CE H 0CD H 0CC H 0CB H 0CA H 0C9 H 0C8 H 0C8 H T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0 T2CON These bits are not used in combination with timer 2. Timer 2 control register.
Page 88 On-Chip Peripheral Components 7.5.2 Compare Function of Registers CRC, CC1 to CC3 The compare function of a timer/register combination can be described as follows. The 16-bit value stored in a compare/capture register is compared with the contents of the timer register. lf the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin, and an interrupt is requested.
Page 89 On-Chip Peripheral Components Figure 7-35 Port Latch in Compare Mode 0 Figure 7-36 Timer 2 with Registers CCx in Compare Mode 0 (CCx stands for CRC, CC1 to CC3; IEXx stands for IEX3 to IEX6) Semiconductor Group...
Page 90 On-Chip Peripheral Components Timer Count = FFFF Timer Count = Contents Compare Value Timer 2 Timer Count = Reload Value Interrupt can be generated on overflow Compare Output (P1.x/CCx) MCT01906 Interrupt can be generated on compare-match Figure 7-37 Function of Compare Mode 0 Modulation Range in Compare Mode 0 Generally it can be said that for every PWM generation in compare mode 0 with n-bit wide compare registers there are 2...
Page 91 On-Chip Peripheral Components Figure 7-38 Modulation Range of a PWM Signal, Generated with a Timer 2/CCx Register Combination in Compare Mode 0 The following example shows how to calculate the modulation range for a PWM signal. To calculate with reasonable numbers, a reduction of the resolution to 8-bit is used. Otherwise (for the maximum resolution of 16-bit) the modulation range would be so severely limited that it would be negligible.
Page 92 On-Chip Peripheral Components 7.5.2.2 Compare Mode 1 In compare mode 1, the software adaptively determines the transition of the output signal. lt is commonly used when output signals are not related to a constant signal period (as in a standard PWM generation) but must be controlled very precisely with high resolution and without jitter.
Page 93 On-Chip Peripheral Components Figure 7-39 Timer 2 with Registers CCx in Compare Mode 1 (CCx stands for CRC, CC1 to CC3; IEXx stands for IEX3 to IEX6) Semiconductor Group...
Page 94 On-Chip Peripheral Components Figure 7-40 Special Function Register CCEN 0C1 H COCAH3 COCAL3 COCAH2 COCAI2 COCAH1 COCAL1 COCAH0 COCAL0 CCEN Compare/capture enable register selects compare or capture function for register CRC, CC1 to CC3. Function COCAH0 COCAL0 Compare/capture mode for CRC register Compare/capture disabled Capture on falling/rising edge at pin P1.0/INT3/CC0...
Page 95 On-Chip Peripheral Components The compare interrupt can be used very effectively to change the contents of the compare registers or to determine the level of the port outputs for the next "compare match". The principle is, that the internal compare signal (generated at a match between timer count and register contents) not only manipulates the compare output but also sets the corresponding interrupt request flag.
Page 96 On-Chip Peripheral Components The second configuration which should be noted is when compare function is combined with negative transition activated interrupts. lf the port latch of port P1.0 contains a 1, the interrupt request flags IEX2 will immediately be set after enabling the compare mode for the CRC register. The reason is that first the external interrupt input is controlled by the pin’s level.
Page 97 On-Chip Peripheral Components Figures 7-41 and 7-42 show functional diagrams of the capture function of timer 2. Figure 7-41 illustrates the operation of the CRC register, while figure 7-42 shows the operation of the compare/ capture registers 1 to 3. The two capture modes can be established individually for each capture register by bits in SFR CCEN (compare/capture enable register).
Page 98 On-Chip Peripheral Components Figure 7-42 Capture with Registers CC1 to CC3 Power Saving Modes For significantly reducing power consumption, the SAB 80(C)515/80(C)535 provides two Power Saving Modes: – The Power-Down Mode Operation of the component stops completely, the oscillator is turned off. Only the internal RAM is supplied with a very low standby current.
Page 99 On-Chip Peripheral Components 7.6.1 Power Saving Modes of the SAB 80515/80535 The SAB 80515/80535 allows a reduction of the power consumption using the power-down mode. 7.6.1.1 Power-Down Mode of the SAB 80515/80535 The power-down mode in the SAB 80515/80535 allows a reduction of , to zero while saving 40 bytes of the on-chip RAM through a backup supply connected to the pin.
Page 100 On-Chip Peripheral Components 7.6.2 Power Saving Modes of the SAB 80515/80535 Dlfferences between the Power-Down Modes of the SAB 80C515/80C535 and the SAB 80515/ 80535 The power-down mode of the SAB 80515/80535 allows retention of 40 bytes on-chip RAM through a backup supply connected to the pin.
Page 101 On-Chip Peripheral Components 7.6.2.1 Power-Down Mode of the SAB 80C515/80C535 In the power-down mode, the on-chip oscillator is stopped. Therefore, all functions are stopped, only the contents of the on-chip RAM and the SFR’s are held. The port pins controlled by their port latches output the values that are held by their SFR’S.
Page 102 On-Chip Peripheral Components 7.6.2.2 Idle Mode of the SAB 80C515/80C535 In idle mode the oscillator of the SAB 80C515/80C535 continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the serial channel, the A/D converter and all timers, except for the watchdog timer, are further provided with the clock.
Page 103 On-Chip Peripheral Components Table 7-10 Status of External Pins During Idle and Power-Down Mode Outputs Last Instruction Executed from Last Instruction Executed from Internal Code Memory External Code Memory Idle Power-down Idle Power-down High High PSEN High High Port 0 Data Data Float...
Page 104 On-Chip Peripheral Components The following instruction sequence may serve as an exemple: PCON,#00000001B ;Set bit IDLE, ;bit IDLS must not be set PCON,#00100000B ;Set bit IDLS, ;bit IDLE must not be set The instruction that sets bit IDLS is the last instruction executed before going into idle mode. Terminating the Idle Mode –...
Page 105 On-Chip Peripheral Components Watchdog Timer As a means of graceful recovery from software or hardware upset a watchdog timer is provided in the SAB 80(C)515/80(C)535. lf the software fails to clear the watchdog timer at least every 65532 µs, an internal hardware reset will be initiated. The software can be designed such that the watchdog times out if the program does not progress properly.
Page 106 On-Chip Peripheral Components Figure 7-46 Special Function Register IEN1 0BF H 0BE H 0BD H 0BC H 0BB H 0BA H 0B9 H 0B8 H 0B8 H EXEN2 SWDT EADC IEN1 These bits are not used by the watchdog timer. Function SWDT Watchdog timer start/refresh flag.
Page 107 On-Chip Peripheral Components Oscillator and Clock Circuit XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter which can be configured with off-chip components as a Pierce oscillator. The oscillator, in any case, drives the internal clock generator. The clock generator provides the internal clock signals to the chip at half the oscillator frequency.
Page 108 On-Chip Peripheral Components 7.8.2.1 Driving the SAB 80515/80535 from External Source For driving the SAB 80515/80535 from an external clock source, the external clock signal is to be applied to XTAL2. A pullup resistor is recommended to increase the noise margin, but is optional if the output high level of the driving gate meets the V specification of XTAL2.
Page 109 On-Chip Peripheral Components 7.8.2.2 Driving the SAB 80C515/80C535 from External Source For driving the SAB 80C515/80C535 from an external clock source, the external clock signal is to be applied to XTAL2, as shown in figure 7-52. A pullup resistor is recommended, but is optional if the output high level of the driving gate corresponds to the V specification of XTAL2.
Page 110 On-Chip Peripheral Components System Clock Output For peripheral devices requiring a system clock, the SAB 80(C)515/80(C)535 provides a clock output signal derived from the oscillator frequency as an alternate output function on pin P1.6/ CLKOUT. lf bit CLK is set (bit 6 of special function register ADCON, see figure 7-53), a clock signal with 1/12 of the oscillator frequency is gated to pin P1.6/CLKOUT.
Page 111 On-Chip Peripheral Components Figure 7-54 Timing Diagram - System Clock Output Semiconductor Group...
Page 112 Interrupt System Interrupt System The SAB 80C515/80C535 provides 12 interrupt sources with four priority levels. Five interrupts can be generated by the on-chip peripherals (i.e. timer 0, timer 1, timer 2, compare timer, serial interface and A/D converter), and seven interrupts may be triggered externally (see figure 8.1).
Page 113 Interrupt System Figure 8-1 a) Interrupt Structure of the SAB 80(C)515/80(C)535 Semiconductor Group...
Page 114 Interrupt System Figure 8-1 b) Interrupt Structure of the SAB 80(C)515/80(C)535 (cont’d) Semiconductor Group...
Page 115 Interrupt System Figure 8-2 Special Function Register IEN0 (Address 0A8 H ) 0AF H 0AE H 0AD H 0AC H 0AB H 0AA H 0A9 H 0A8 H 0A8 H IEN0 This bit is not used for interrupt control. Function Enables or disables external interrupt 0.
Page 116 Interrupt System Figure 8-3 Special Function Register IEN1 (Address 0B8 H ) 0BF H 0BE H 0BD H 0BC H 0BB H 0BA H 0B9 H 0B8 H 0B8 H EXEN2 SWDT EADC IEN1 This bit is not used for interrupt control. Function EADC Enables or disables the A/D converter interrupt.
Page 117 Interrupt System The serial port interrupt is generated by a logical OR of flag RI and Tl in SFR SCON (see figure 7-7). Neither of these flags is cleared by hardware when the service routine is vectored too. In fact, the service routine will normally have to determine whether it was the receive interrupt flag or the transmission interrupt flag that generated the interrupt, and the bit will have to be cleared by software.
Page 118 Interrupt System The external interrupt 2 (INT2/) can be either positive or negative transition-activated depending on bit I2FR in register T2CON (see figure 8-5). The flag that actually generates this interrupt is bit IEX2 in register IRCON. lf an interrupt 2 is generated, flag IEX2 is cleared by hardware when the service routine is vectored too.
Page 119 Interrupt System Figure 8-6 Special Function Register IRCON (Address 0C0 H ) 0C7 H 0C6 H 0C5 H 0C4 H 0C3 H 0C2 H 0C1 H 0C0 H 0C0 H EXF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC IRCON Function IADC A/D converter interrupt request flag.
Page 120 Interrupt System All of these bits that generate interrupts can be set or cleared by software, with the same result as if they had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be cancelled by software. The only exceptions are the request flags IE0 and lE1. lf the external interrupts 0 and 1 are programmed to be level-activated, IE0 and lE1 are controlled by the external source via pin INT0 and INT1, respectively.
Page 121 Interrupt System lf two or more requests of different priority levels are received simultaneously, the request of the highest priority is serviced first. lf requests of the same priority level are received simultaneously, an internal polling sequence determines which request is to be serviced first. Thus, within each priority level there is a second priority structure determined by the polling sequence, as follows (see figure 8-8): –...
Page 122 Interrupt System Figure 8-8 Priority-Within-Level Structure → High Priority Interrupt source IADC High IEX2 ↓ IEX3 IEX4 RI + TI IEX5 TF2 + EXF2 IEX6 Note: This "priority-within-level" structure is only used to resolve simultaneous requests of the same priority level. How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle.
Page 123 Interrupt System The polling cycle is repeated with each machine cycle, and the values polled are the values that were present at S5P2 of the previous machine cycle. Note that if any interrupt flag is active but not being responded to for one of the conditions already mentioned, or if the flag is no longer active when the blocking condition is removed, the denied interrupt will not be serviced.
Page 124 Interrupt System Table 8-2 Interrupt Sources and Vectors Interrupt Request Flags Interrupt Vector Address Interrupt Source 0003 H External interrupt 0 000B H Timer overflow 0013 H External interrupt 1 001B H Timer 1 overflow RI/TI 0023 H Serial channel TF2/EXF2 002B H Timer 2 overflow/ext.
Page 125 Interrupt System External Interrupts The external interrupts 0 and 1 can be programmed to be level-activated or negative-transition activated by setting or clearing bit IT0 or IT1, respectively, in register TCON (see figure 8-4). lf ITx = 0 (x = 0 or 1), external interrupt x is triggered by a detected low level at the INTx pin. lf ITx = 1, external interrupt x is negative edge-triggered.
Page 126 Interrupt System Figure 8-10 External Interrupt Detection Response Time lf an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. lf the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed.
Page 127 Instruction Set Instruction Set The SAB 80(C)515/80(C)535 instruction set includes 111 instructions, 49 of which are single-byte, 45 two-byte and 17 three-byte instructions. The instruction opcode format consists of a function mnemonic followed by a ”destination, source” operand field. This field specifies the data type and addressing method(s) to be used.
Page 128 Instruction Set Table 9-1 Addressing Modes and Associated Memory Spaces Addressing Modes Associated Memory Spaces Register addressing R0 through R7 of selected register bank, ACC, B, CY (Bit), DPTR Direct addressing Lower 128 bytes of internal RAM, special function registers Immediate addressing Program memory Register indirect addressing...
Page 129 Instruction Set The Bit Manipulation Instructions allow: – set bit – clear bit – complement bit – jump if bit is set – jump if bit is not set – jump if bit is set and clear bit – move bit from / to carry Addressable bits, or their complements, may be logically AND-ed or OR-ed with the contents of the carry flag.
Page 130 Instruction Set General-Purpose Transfers – MOV performs a bit or byte transfer from the source operand to the destination operand. – PUSH increments the SP register and then transfers a byte from the source operand to the stack location currently addressed by SP. –...
Page 131 Instruction Set Subtraction – SUBB (subtract with borrow) subtracts the second source operand from the the first operand (the accumulator), subtracts one (1) if CY is set and returns the result to A. – DEC (decrement) subtracts one (1) from the source operand and returns the result to the operand.
Page 132 Instruction Set 9.2.3 Logic The SAB 80(C)515/80(C)535 performs basic logic operations on both bit and byte operands. Single-Operand Operations – CLR sets A or any directly addressable bit to zero (0). – SETB sets any directly bit-addressable bit to one (1). –...
Page 133 Instruction Set Unconditional Calls, Returns and Jumps Unconditional calls, returns and jumps transfer control from the current value of the program counter to the target address. Both direct and indirect transfers are supported. – ACALL and LCALL push the address of the next instruction onto the stack and then transfer control to the target address.
Page 134 Instruction Set Instruction Definitions All 111 instructions of the SAB 80(C)515/80(C)535 can essentially be condensed to 54 basic operations, in the following alphabetically ordered according to the operation mnemonic section. Instruction Flag Instruction Flag SETB C ADDC CLR C SUBB CPL C ANL C,bit ANL C,/bit...
Page 135 Instruction Set Notes on Data Addressing Modes Working register R0-R7 direct 128 internal RAM locations, any l/O port, control or status register Indirect internal or external RAM location addressed by register R0 or R1 #data 8-bit constant included in instruction #data 16 16-bit constant included as bytes 2 and 3 of instruction 128 software flags, any bitaddressable l/O pin, control or status bit...
Page 136 Instruction Set ACALL addr11 Function: Absolute call Description: ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the stack pointer twice.
Page 137 Instruction Set A, <src-byte> Function: Description: ADD adds the byte variable indicated to the accumulator, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occurred.
Page 138 Instruction Set A, @Ri Operation: (A) ← (A) + ((Ri)) Encoding: 0 0 1 0 0 1 1 i Bytes: Cycles: A, #data Operation: (A) ← (A) + #data Encoding: 0 0 1 0 0 1 0 0 immediate data Bytes: Cycles: Semiconductor Group...
Page 139 Instruction Set ADDC A, < src-byte> Function: Add with carry Description: ADDC simultaneously adds the byte variable indicated, the carry flag and the accumulator contents, leaving the result in the accumulator. The carry and auxiliary carry flags are set, respectively, if there is a carry out of bit 7 or bit 3, and cleared otherwise.
Page 140 Instruction Set ADDC A, @Ri Operation: ADDC (A) ← (A) + (C) + ((Ri)) Encoding: 0 0 1 1 0 1 1 i Bytes: Cycles: ADDC A, #data Operation: ADDC (A) ← (A) + (C) + #data Encoding: 0 0 1 1 0 1 0 0 immediate data Bytes:...
Page 141 Instruction Set AJMP addr11 Function: Absolute jump Description: AJMP transfers program execution to the indicated address, which is formed at run- time by concatenating the high-order five bits of the PC ( after incrementing the PC twice), op code bits 7-5, and the second byte of the instruction. The destination must therefore be within the same 2K block of program memory as the first byte of the instruction following AJMP.
Page 142 Instruction Set <dest-byte>, <src-byte> Function: Logical AND for byte variables Description: ANL performs the bitwise logical AND operation between the variables indicated and stores the results in the destination variable. No flags are affected. The two operands allow six addressing mode combinations. When the destination is a accumulator, the source can use register, direct, register-indirect, or immediate addressing;...
Page 143 Instruction Set A,direct Operation: (A) ← (A) ∧ (direct) Encoding: 0 1 0 1 0 1 0 1 direct address Bytes: Cycles: A, @Ri Operation: (A) ← (A) ∧ ((Ri)) Encoding: 0 1 0 1 0 1 1 i Bytes: Cycles: A, #data Operation:...
Page 144 Instruction Set direct, #data Operation: (direct) ← (direct) ∧ #data Encoding: 0 1 0 1 0 0 1 1 direct address immediate data Bytes: Cycles: Semiconductor Group...
Page 145 Instruction Set C, <src-bit> Function: Logical AND for bit variables Description: If the Boolean value of the source bit is a logic 0 then clear the carry flag; otherwise leave the carry flag in its current state. A slash (”/” preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected .
Page 146 Instruction Set CJNE <dest-byte >, < src-byte >, rel Function: Compare and jump if not equal Description: CJNE compares the magnitudes of the tirst two operands, and branches if their values are not equal. The branch destination is computed by adding the signed relative displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction.
Page 147 Instruction Set CJNE A,direct,rel (PC) ← (PC) + 3 Operation: if (A) < > (direct) then (PC) ← (PC) + relative offset if (A) < (direct) then (C) ←1 else (C) ← 0 Encoding: 1 0 1 1 0 1 0 1 direct address rel.
Page 148 Instruction Set CJNE @Ri, #data,rel (PC) ← (PC) + 3 Operation: if ((Ri)) < > data then (PC) ← (PC) + relative offset if ((Ri)) < data then (C) ← 1 else (C) ← 0 Encoding: 1 0 1 1 0 1 1 i immediate data rel.
Page 149 Instruction Set Function: Clear accumulator Description: The accumulator is cleared (all bits set to zero). No flags are affected. Example: The accumulator contains 5C H (01011100B). The instruction will leave the accumulator set to 00 H (00000000B). Operation: (A) ← 0 Encoding: 1 1 1 0 0 1 0 0...
Page 150 Instruction Set Function: Clear bit Description: The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on the carry flag or any directly addressable bit. Example: Port 1 has previously been written with 5D H (01011101B). The instruction P1.2 will leave the port set to 59 H (01011001B).
Page 151 Instruction Set Function: Complement accumulator Description: Each bit of the accumulator is logically complemented (one’s complement). Bits which previously contained a one are changed to zero and vice versa. No flags are affected. Example: The accumulator contains 5C H (01011100B). The instruction will leave the accumulator set to 0A3 H (10100011 B).
Page 152 Instruction Set Function: Complement bit Description: The bit variable specified is complemented. A bit which had been a one is changed to zero and vice versa. No other flags are affected. CPL can operate on the carry or any directly addressable bit. Note: When this instruction is used to modify an output pin, the value used as the original data will be read from the output data latch, not the input pin.
Page 153 Instruction Set Function: Decimal adjust accumulator for addition Description: DA A adjusts the eight-bit value in the accumulator resulting from the earlier addition of two variables (each in packed BCD format), producing two four-bit digits. Any ADD or ADDC instruction may have been used to perform the addition. If accumulator bits 3-0 are greater than nine (xxxx1010-xxxx1111), or if the AC flag is one, six is added to the accumulator producing the proper BCD digit in the low- order nibble.
Page 154 Instruction Set BCD variables can be incremented or decremented by adding 01 H or 99 H . If the accumulator initially holds 30 H (representing the digits of 30 decimal), then the instruction sequence A, #99 H will leave the carry set and 29 H in the accumulator, since 30 + 99 = 129. The low- order byte of the sum can be interpreted to mean 30 –...
Page 155 Instruction Set byte Function: Decrement Description: The variable indicated is decremented by 1. An original value of 00 H will underflow to 0FF H . No flags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Page 156 Instruction Set direct Operation: (direct) ← (direct) – 1 Encoding: 0 0 0 1 0 1 0 1 direct address Bytes: Cycles: Operation: ((Ri)) ← ((Ri)) – 1 Encoding: 0 0 0 1 0 1 1 i Bytes: Cycles: Semiconductor Group...
Page 157 Instruction Set Instruction Set Function: Divide Description: DIV AB divides the unsigned eight-bit integer in the accumulator by the unsigned eight-bit integer in register B. The accumulator receives the integer part of the quotient; register B receives the integer remainder. The carry and OV flags will be cleared.
Page 158 Instruction Set DJNZ <byte>, < rel-addr> Function: Decrement and jump if not zero Description: DJNZ decrements the location indicated by 1, and branches to the address indicated by the second operand if the resulting value is not zero. An original value of 00 H will underflow to 0FF H .
Page 159 Instruction Set DJNZ Rn,rel Operation: DJNZ (PC) ← (PC) + 2 (Rn) ← (Rn) – 1 if (Rn) > 0 or (Rn) < 0 then (PC) ← (PC) + rel Encoding: 1 1 0 1 1 r r r rel. address Bytes: Cycles: DJNZ...
Page 160 Instruction Set <byte> Function: Increment Description: INC increments the indicated variable by 1. An original value of 0FF H will overflow to 00 H . No flags are affected. Three addressing modes are allowed: register, direct, or register-indirect. Note: When this instruction is used to modify an output port, the value used as the original port data will be read from the output data latch, not the input pins.
Page 161 Instruction Set direct Operation: (direct) ← (direct) + 1 Encoding: 0 0 0 0 0 1 0 1 direct address Bytes: Cycles: Operation: ((Ri)) ← ((Ri)) + 1 Encoding: 0 0 0 0 0 1 1 i Bytes: Cycles: Semiconductor Group...
Page 162 Instruction Set DPTR Function: Increment data pointer Description: Increment the 16-bit data pointer by 1. A 16-bit increment (modulo 2 ) is performed; an overflow of the low-order byte of the data pointer (DPL) from 0FF H to 00 H will increment the high-order byte (DPH).
Page 163 Instruction Set bit,rel Function: Jump if bit is set Description: If the indicated bit is a one, jump to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
Page 164 Instruction Set bit,rel Function: Jump if bit is set and clear bit Description: If the indicated bit is one, branch to the address indicated; otherwise proceed with the next instruction. In either case, clear the designated bit. The branch destination is computed by adding the signed relative displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
Page 165 Instruction Set Function: Jump if carry is set Description: If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative- displacement in the second instruction byte to the PC, after incrementing the PC twice.
Page 166 Instruction Set @A + DPTR Function: Jump indirect Description: Add the eight-bit unsigned contents of the accumulator with the sixteen-bit data pointer, and load the resulting sum to the program counter. This will be the address for subsequent instruction fetches. Sixteen-bit addition is performed (modulo 2 ): a carry-out from the low-order eight bits propagates through the higher-order bits.
Page 167 Instruction Set bit,rel Function: Jump if bit is not set Description: If the indicated bit is a zero, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction.
Page 168 Instruction Set Function: Jump if carry is not set Description: If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice to point to the next instruction.
Page 169 Instruction Set Function: Jump if accumulator is not zero Description: If any bit of the accumulator is a one, branch to the indicated address; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice.
Page 170 Instruction Set Function: Jump if accumulator is zero Description: If all bits of the accumulator are zero, branch to the address indicated; otherwise proceed with the next instruction. The branch destination is computed by adding the signed relative-displacement in the second instruction byte to the PC, after incrementing the PC twice.
Page 171 Instruction Set LCALL addr16 Function: Long call Description: LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the stack pointer by two.
Page 172 Instruction Set LJMP addr16 Function: Long jump Description: LJMP causes an unconditional branch to the indicated address, by loading the high- order and low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination may therefore be anywhere in the full 64K program memory address space.
Page 173 Instruction Set <dest-byte>, <src-byte> Function: Move byte variable Description: The byte variable indicated by the second operand is copied into the location specified by the first operand. The source byte is not affected. No other register or flag is affected. This is by far the most flexible operation.
Page 174 Instruction Set A,@Ri Operation: (A) ← ((Ri)) Encoding: 1 1 1 0 0 1 1 i Bytes: Cycles: A, #data Operation: (A) ← #data Encoding: 0 1 1 1 0 1 0 0 immediate data Bytes: Cycles: Rn,A Operation: (Rn) ← (A) Encoding: 1 1 1 1 1 r r r...
Page 175 Instruction Set Rn, #data Operation: (Rn) ← #data Encoding: 0 1 1 1 1 r r r immediate data Bytes: Cycles: direct,A Operation: (direct) ← (A) Encoding: 1 1 1 1 0 1 0 1 direct address Bytes: Cycles: direct,Rn Operation: (direct) ←...
Page 176 Instruction Set direct, @ Ri Operation: (direct) ← ((Ri)) Encoding: 1 0 0 0 0 1 1 i direct address Bytes: Cycles: direct, #data Operation: (direct) ← #data Encoding: 0 1 1 1 0 1 0 1 direct address immediate data Bytes: Cycles: @ Ri,A...
Page 177 Instruction Set @ Ri,#data Operation: ((Ri)) ← #data Encoding: 0 1 1 1 0 1 1 i immediate data Bytes: Cycles: Semiconductor Group...
Page 178 Instruction Set <dest-bit>, <src-bit> Function: Move bit data Description: The Boolean variable indicated by the second operand is copied into the location specified by the first operand. One of the operands must be the carry flag; the other may be any directly addressable bit. No other register or flag is affected. Example: The carry flag is originally set.
Page 179 Instruction Set DPTR, #data16 Function: Load data pointer with a 16-bit constant Description: The data pointer is loaded with the 16-bit constant indicated. The 16 bit constant is loaded into the second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the third byte (DPL) holds the low-order byte.
Page 180 Instruction Set MOVC A, @A + <base-reg> Function: Move code byte Description: The MOVC instructions load the accumulator with a code byte, or constant from program memory. The address of the byte fetched is the sum of the original unsigned eight-bit accumulator contents and the contents of a sixteen-bit base register, which may be either the data pointer or the PC.
Page 181 Instruction Set MOVC A, @A + PC Operation: MOVC (PC) ← (PC) + 1 (A) ← ((A) + (PC)) Encoding: 1 0 0 0 0 0 1 1 Bytes: Cycles: Semiconductor Group...
Page 182 Instruction Set MOVX <dest-byte>, <src-byte> Function: Move external Description: The MOVX instructions transfer data between the accumulator and a byte of external data memory, hence the ”X” appended to MOV. There are two types of instructions, differing in whether they provide an eight bit or sixteen-bit indirect address to the external data RAM.
Page 183 Instruction Set MOVX A,@Ri Operation: MOVX (A) ← ((Ri)) Encoding: 1 1 1 0 0 0 1 i Bytes: Cycles: MOVX A,@DPTR Operation: MOVX (A) ← ((DPTR)) Encoding: 1 1 1 0 0 0 0 0 Bytes: Cycles: MOVX @Ri,A Operation: MOVX ((Ri)) ←...
Page 184 Instruction Set Function: Multiply Description: MUL AB multiplies the unsigned eight-bit integers in the accumulator and register B. The low-order byte of the sixteen-bit product is left in the accumulator, and the high-order byte in B. If the product is greater than 255 (0FF H ) the overflow flag is set;...
Page 185 Instruction Set Function: No operation Description: Execution continues at the following instruction. Other than the PC, no registers or flags are affected. Example: It is desired to produce a low-going output pulse on bit 7 of port 2 lasting exactly 5 cycles.
Page 186 Instruction Set <dest-byte> <src-byte> Function: Logical OR for byte variables Description: ORL performs the bitwise logical OR operation between the indicated variables, storing the results in the destination byte. No flags are affected . The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing;...
Page 187 Instruction Set A,direct Operation: (A) ← (A) ∨ (direct) Encoding: 0 1 0 0 0 1 0 1 direct address Bytes: Cycles: A,@Ri Operation: (A) ← (A) ∨ ((Ri)) Encoding: 0 1 0 0 0 1 1 i Bytes: Cycles: A,#data Operation: (A) ←...
Page 188 Instruction Set direct, #data Operation: (direct) ← (direct) ∨ #data Encoding: 0 1 0 0 0 0 1 1 direct address immediate data Bytes: Cycles: Semiconductor Group...
Page 189 Instruction Set C, <src-bit> Function: Logical OR for bit variables Description: Set the carry flag if the Boolean value is a logic 1; leave the carry in its current state otherwise. A slash (”/”) preceding the operand in the assembly language indicates that the logical complement of the addressed bit is used as the source value, but the source bit itself is not affected.
Page 190 Instruction Set direct Function: Pop from stack Description: The contents of the internal RAM location addressed by the stack pointer is read, and the stack pointer is decremented by one. The value read is the transfer to the directly addressed byte indicated. No flags are affected. Example: The stack pointer originally contains the value 32 H , and internal RAM locations 30 H through 32 H contain the values 20 H , 23 H , and 01 H , respectively.
Page 191 Instruction Set PUSH direct Function: Push onto stack Description: The stack pointer is incremented by one. The contents of the indicated variable is then copied into the internal RAM location addressed by the stack pointer. Otherwise no flags are affected. Example: On entering an interrupt routine the stack pointer contains 09 H .
Page 192 Instruction Set Function: Return from subroutine Description: RET pops the high and low-order bytes of the PC successively from the stack, decrementing the stack pointer by two. Program execution continues at the resulting address, generally the instruction immediately following an ACALL or LCALL.
Page 193 Instruction Set RETI Function: Return from interrupt Description: RETI pops the high and low-order bytes of the PC successively from the stack, and restores the interrupt logic to accept additional interrupts at the same priority level as the one just processed. The stack pointer is left decremented by two. No other registers are affected;...
Page 194 Instruction Set Function: Rotate accumulator left Description: The eight bits in the accumulator are rotated one bit to the left. Bit 7 is rotated into the bit 0 position. No flags are affected. Example: The accumulator holds the value 0C5 H (11000101B). The instruction leaves the accumulator holding the value 8B H (10001011B) with the carry unaffected.
Page 195 Instruction Set Function: Rotate accumulator left through carry flag Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves into the carry flag; the original state of the carry flag moves into the bit 0 position.
Page 196 Instruction Set Function: Rotate accumulator right Description: The eight bits in the accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position. No flags are affected. Example: The accumulator holds the value 0C5 H (11000101B). The instruction leaves the accumulator holding the value 0E2 H (11100010B) with the carry unaffected.
Page 197 Instruction Set Function: Rotate accumulator right through carry flag Description: The eight bits in the accumulator and the carry flag are together rotated one bit to the right. Bit 0 moves into the carry flag; the original value of the carry flag moves into the bit 7 position.
Page 198 Instruction Set SETB <bit> Function: Set bit Description: SETB sets the indicated bit to one. SETB can operate on the carry flag or any directiy addressable bit. No other flags are affected. Example: The carry flag is cleared. Output port 1 has been written with the value 34 H (00110100B).
Page 199 Instruction Set SJMP Function: Short jump Description: Program control branches unconditionally to the address indicated. The branch destination is computed by adding the signed displacement in the second instruction byte to the PC, after incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding this instruction to 127 bytes following it.
Page 200 Instruction Set SUBB A, <src-byte> Function: Subtract with borrow Description: SUBB subtracts the indicated variable and the carry flag together from the accumulator, leaving the result in the accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was needed for the previous step in a multiple precision subtraction, so the carry is subtracted from the accumulator along with the source operand).
Page 201 Instruction Set SUBB A,direct Operation: SUBB (A) ← (A) – (C) – (direct) Encoding: 1 0 0 1 0 1 0 1 direct address Bytes: Cycles: SUBB A, @ Ri Operation: SUBB (A) ← (A) – (C) – ((Ri)) Encoding: 1 0 0 1 0 1 1 i Bytes:...
Page 202 Instruction Set SWAP Function: Swap nibbles within the accumulator Description: SWAP A interchanges the low and high-order nibbles (four-bit fields) of the accumulator (bits 3-0 and bits 7-4). The operation can also be thought of as a four- bit rotate instruction. No flags are affected. Example: The accumulator holds the value 0C5 H (11000101B).
Page 203 Instruction Set A, <byte> Function: Exchange accumulator with byte variable Description: XCH loads the accumulator with the contents of the indicated variable, at the same time writing the original accumulator contents to the indicated variable. The source/ destination operand can use register, direct, or register-indirect addressing. Example: R0 contains the address 20 H .
Page 204 Instruction Set A, @ Ri Operation: ← → ((Ri)) Encoding: 1 1 0 0 0 1 1 i Bytes: Cycles: Semiconductor Group...
Page 205 Instruction Set XCHD A,@Ri Function: Exchange digit Description: XCHD exchanges the low-order nibble of the accumulator (bits 3-0, generally representing a hexadecimal or BCD digit), with that of the internal RAM location indirectly addressed by the specified register. The high-order nibbles (bits 7-4) of each register are not affected.
Page 206 Instruction Set <dest-byte>, <src-byte> Function: Logical Exclusive OR for byte variables Description: XRL performs the bitwise logical Exclusive OR operation between the indicated variables, storing the results in the destination. No flags are affected. The two operands allow six addressing mode combinations. When the destination is the accumulator, the source can use register, direct, register-indirect, or immediate addressing;...
Page 207 Instruction Set A,direct Operation: (A) ← (A) (direct) Encoding: 0 1 1 0 0 1 0 1 direct address Bytes: Cycles: A, @ Ri Operation: (A) ← (A) ((Ri)) Encoding: 0 1 1 0 0 1 1 i Bytes: Cycles: A, #data Operation: (A) ←...
Page 208 Instruction Set direct, #data Operation: (direct) ← (direct) #data Encoding: 0 1 1 0 0 0 1 1 direct address immediate data Bytes: Cycles: Semiconductor Group...
Page 209 Instruction Set Instruction Set Summary Mnemonic Description Byte Cycle Arithmetic Operations A,Rn Add register to accumulator A,direct Add direct byte to accumulator A, @Ri Add indirect RAM to accumulator A,#data Add immediate data to accumulator ADDC A,Rn Add register to accumulator with carry flag ADDC A,direct Add direct byte to A with carry flag ADDC A, @Ri...
Page 210 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Byte Cycle Logic Operations A,Rn AND register to accumulator A,direct AND direct byte to accumulator A,@Ri AND indirect RAM to accumulator A,#data AND immediate data to accumulator direct,A AND accumulator to direct byte direct,#data AND immediate data to direct byte A,Rn...
Page 211 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Byte Cycle Data Transfer A,Rn Move register to accumulator A,direct Move direct byte to accumulator A,@Ri Move indirect RAM to accumulator A,#data Move immediate data to accumulator Rn,A Move accumulator to register Rn,direct Move direct byte to register Rn,#data...
Page 212 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Byte Cycle Boolean Variable Manipulation Clear carry flag Clear direct bit SETB Set carry flag SETB Set direct bit Complement carry flag Complement direct bit C,bit AND direct bit to carry flag C,/bit AND complement of direct bit to carry C,bit...
Page 213 Instruction Set Instruction Set Summary (cont’d) Mnemonic Description Byte Cycle Program and Machine Control (cont’d) CJNE A,#data,rel Compare immediate to A and jump if not equal CJNE Rn,#data rel Compare immed. to reg. and jump if not equal CJNE @Ri,#data,rel Compare immed.
Page 214 (for 12, 16, 20 MHz) – 40 to 85 °C (for 12, 16 MHz) The SAB 80C515/80C535 is a powerful member of the Siemens SAB 8051 family of 8-bit microcontrollers. It is designed in Siemens ACMOS technology and is functionally compatible with the SAB 80515/80535 devices designed in MYMOS technology.
Page 215 Device Specifications Semiconductor Group...
Page 216 Device Specifications Ordering Information Type Ordering Package Description Code 8-Bit CMOS Microcontroller SAB 80C515-N Q 67120-DXXXX P-LCC-68 with mask-programmable ROM, 12 MHz SAB 80C535-N Q 67120-C0508 P-LCC-68 for external memory, 12 MHz SAB 80C515-N-T40/85 Q 67120-DXXXX P-LCC-68 with mask-programmable ROM, 12 MHz ext.
Page 217 Device Specifications Pin Configuration (P-LCC-68) Semiconductor Group...
Page 218 Device Specifications RESET P5.7 N.C. P0.7 / AD7 VAREF P0.6 / AD6 VAGND P0.5 / AD5 P6.7 / AIN7 P0.4 / AD4 P6.6 / AIN6 P0.3 / AD3 P6.5 / AIN5 P0.2 / AD2 P6.4 / AIN4 P0.1 / AD1 SAB 80C535 / 80C515 P6.3 / AIN3 P0.0 / AD0...
Page 219 Device Specifications Logic Symbol Semiconductor Group...
Page 220 Device Specifications Pin Definitions and Functions Symbol Input (I) Function P-LCC-68 P-MQFP-80 Output (O) P4.0-P4.7 1-3, 5-9 72-74, Port 4 76-80 is an 8-bit bidirectional I/O port with internal pullup resistors. Port 4 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs.
Page 221 Device Specifications Pin Definitions and Functions (cont’d) Symbol Input (I) Function P-LCC-68 P-MQFP-80 Output (O) P3.0-P3.7 21-28 15-22 Port 3 is an 8-bit bidirectional I/O port with internal pullup resistors. Port 3 pins that have1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs.
Page 222 Device Specifications Pin Definitions and Functions (cont’d) Symbol Input (I) Function P-LCC-68 P-MQFP-80 Output (O) P1.7-P1.0 29-36 24-31 Port 1 is an 8-bit bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs.
Page 223 Device Specifications Pin Definitions and Functions (cont’d) Symbol Input (I) Function P-LCC-68 P-MQFP-80 Output (O) XTAL2 XTAL2 XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL1 Output of the inverting oscillator amplifier. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected.
Page 224 Device Specifications Pin Definitions and Functions (cont’d) Symbol Input (I) Function P-LCC-68 P-MQFP-80 Output (O) PSEN The Program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods, except during external data memory accesses.
Page 225 Device Specifications Pin Definitions and Functions (cont’d) Symbol Input (I) Function P-LCC-68 P-MQFP-80 Output (O) P5.7-P5.0 60-67 60-67 Port 5 is an 8-bit bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs.
Page 226 Device Specifications Figure 1 Block Diagram Semiconductor Group...
Page 227 Device Specifications Functional Description The members of the SAB 80515 family of microcontrollers are: – SAB 80C515: Microcontroller, designed in Siemens ACMOS technology, with 8 Kbyte factory mask-programmable ROM – SAB 80C535: ROM-less version of the SAB 80C515 – SAB 80515:...
Page 228 Device Specifications The SAB 80C515 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15 % three-byte instructions.
Page 229 Device Specifications Figure 2 Memory Address Spaces Semiconductor Group...
Page 230 Device Specifications Special Function Registers All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function registers include arithmetic registers, pointers, and registers that provide an interface between the CPU and the on-chip peripherals. There are also 128 directly addressable bits within the SFR area.
Page 231 Device Specifications Table 1:Special Function Register (cont’d) Address Register Contents Address Register Contents after Reset after Reset reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved IEN1 ADCON 00X0 0000 XX00 0000 ADDAT reserved DAPR reserved reserved reserved...
Page 232 Device Specifications Table 1:Special Function Register (cont’d) Address Register Contents Address Register Contents after Reset after Reset reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Bit-addressable Special Function Register X means that the value is indeterminate and the location is reserved Semiconductor Group...
Page 233 Device Specifications Table 2: Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer A/D- ADCON A/D Converter Control Register 00X0 0000 Converter ADDAT A/D Converter Data Register...
Page 234 Device Specifications Table 2: Special Function Registers- Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset Ports Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6, Analog/Digital Input Pow.Sav.M PCON Power Control Register 000X 0000 odes Serial A/D Converter Control Reg.
Page 235 Device Specifications I/O Ports The SAB 80C515 has six 8-bit I/O ports and one 8-bit input port. Port 0 is an open-drain bidirectional I/O port, while ports 1 to 5 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 5 will be pulled high and will source current when externally pulled low.
Page 236 Device Specifications Timer/Counters The SAB 80C515 contains three 16-bit timers/counters which are useful in many applications for timing and counting. The input clock for each timer/counter is 1/12 of the oscillator frequency in the timer operation or can be taken from an external clock source for the counter operation (maximum count rate is 1/24 of the oscillator frequency).
Page 237 Device Specifications Compare In the compare mode, the 16-bit values stored in the dedicated compare registers are compared to the contents of the timer 2 registers. If the count value in the timer 2 registers matches one of the stored values, an appropriate output signal is generated and an interrupt is requested.
Page 238 Device Specifications Serial Port The serial port of the SAB 80C515 enables full duplex communication between microcontrol- lers or between microcontroller and peripheral devices. The serial port can operate in 4 modes: × × Mode 0: Shift register mode. Serial data enters and exits through R D.
Page 239 Device Specifications Figure 4 Block Diagram of the A/D Converter Semiconductor Group...
Page 240 Device Specifications Interrupt Structure The SAB 80C515 has 12 interrupt vectors with the following vector addresses and request flags: Table 3 Interrupt Sources and Vectors Source (Request Flags) Vector Address Vector 0003 External interrupt 0 000B Timer 0 interrupt 0013 External interrupt 1 001B Timer 1 interrupt...
Page 241 Device Specifications Figure 5 Interrupt Request Sources Semiconductor Group...
Page 242 Device Specifications Figure 6 Interrupt Priority Level Structure Semiconductor Group...
Page 243 Device Specifications Watchdog Timer This feature is provided as a means of graceful recovery from a software upset. After an external reset, the watchdog timer is cleared and stopped. It can be started and cleared by software, but it cannot be stopped during active mode of the device. If the software fails to clear the watchdog timer at least every 65532 machine cycles (about 65 ms if a 12 MHz oscillator frequency is used), an internal reset will be initiated.
Page 244 Device Specifications If the power-down mode and the idle mode are set at the same time, power-down takes prece- dence. Furthermore, register PCON contains two general purpose flags. For example, the flag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation or during an idle.
Page 245 Device Specifications If all timers are stopped and the A/D converter and the serial interface are not running, the maximum power reduction can be achieved. This state is also the test condition for the idle mode I (see DC characteristics, note 5). So the user has to take care which peripheral should continue to run and which has to be stopped during idle mode.
Page 246 Device Specifications When idle mode is used, pin PE must be held on low level. The idle mode is then entered by two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5), the following instruction sets the start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0).
Page 247 Device Specifications Note that PCON is not a bit-addressable register, so the above mentioned sequence for entering the power-down mode is obtained by byte-handling instructions, as shown in the following example: PCON,#00000010 ;Set bit PDE, bit PDS must not be set PCON,#01000000 ;Set bit PDS, bit PDE must not be set The instruction that sets bit PDS is the last instruction executed before going into...
Page 248 Device Specifications Instruction Set The SAB 80C515 / 83C535 has the same instruction set as the industry standard 8051 micro- controller. A pocket guide is available which contains the complete instruction set in functional and hexa- decimal order. Furtheron it provides helpful information about Special Function Registers, In- terrupt Vectors and Assembler Directives.
Page 249 Device Specifications Absolute Maximum Ratings Ambient temperature under bias 0 to 70 °C SAB 80C515 – 40 to 85 °C SAB 80C515-T3 – 65 to 150 °C Storage temperature Voltage on V pins with respect to ground (V – 0.5 to 6.5 V Voltage on any pin with respect to ground (V –...
Page 250 Device Specifications DC Characteristics (cont’d) Parameter Symbol Limit values Unit Test condition min. max. Output low voltage, port 0, 0.45 = 3.2 – ALE, PSEN = – 80 µA Output high voltage, ports – = – 10 µA 1, 2, 3, 4, 5 0.9 V –...
Page 251 Device Specifications Notes for page 249 and 250: 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V of ALE and ports 1, 3, 4 and 5. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation.
Page 252 Device Specifications A/D Converter Characteristics ± CC ± SS ± = 5 V 10 %; V = 0 V; V 5 %; V 0.2 V; AREF AGND I ntAGND ≥ – V 1 V; = 0 to 70 °C for SAB 80C515/80C535 I ntAREF = –...
Page 253 Device Specifications AC Characteristics ± = 5 V 10%; V = 0 V (C for Port 0, ALE and PSEN outputs = 100 pF; for all outputs = 80 pF); = 0 to 70 °C for SAB 80C515/80C535 = – 40 to 85 °C for SAB 80C515/80C535-T40/85 Parameter Symbol Limit values...
Page 254 Device Specifications AC Characteristics (cont’d) Parameter Symbol Limit values Unit 12 MHz clock Variable clock = 3.5 MHz to 12 MHz CLCL min. max. min. max. External Data Memory Characteristics RD pulse width – – CLCL – RLRH WR pulse width –...
Page 255 Device Specifications AC Characteristics (cont’d) Parameter Symbol Limit values Unit Variable clock Frequ. = 3.5 MHz to 12 MHz min. max. External Clock Drive Oscillator period 83.3 CLCL Oscillator frequency CLCL High time – CHCX Low time – CLCX Rise time –...
Page 256 Device Specifications AC Characteristics (cont’d) Parameter Symbol Limit values Unit 12 MHz clock Variable clock = 3.5 MHz to 12 MHz CLCL min. max. min. max. System Clock Timing ALE to CLKOUT – – 40 – LLSH CLCL CLKOUT high time –...
Page 257 Device Specifications AC Characteristics for SAB 80C515-16/80C535-16 ± = 5 V 10 %; V = 0 V (C for Port 0, ALE and PSEN outputs = 100 pF; for all outputs = 80 pF) = 0 to 70 °C for SAB 80C515-16/80C535-16 = –...
Page 258 Device Specifications AC Characteristics (cont’d) Parameter Symbol Limit values Unit 16 MHz clock Variable clock = 3.5 MHz to 16 MHz CLCL min. max. min. max. External Data Memory Characteristics RDpulse width – – 100 – RLRH CLCL WR pulse width –...
Page 259 Device Specifications AC Characteristics (cont’d) Parameter Symbol Limit values Unit Variable clock Frequ. = 3.5 MHz to 16 MHz min. max. External Clock Drive Oscillator period 62.5 CLCL Oscillator frequency CLCL High time – CHCX Low time – CLCX Rise time –...
Page 260 Device Specifications AC Characteristics (cont’d) Parameter Symbol Limit values Unit 16 MHz clock Variable clock = 3.5 MHz to 16 MHz CLCL min. max. min. max. System Clock Timing ALE to CLK OUT – – 40 – LLSH CLCL CLK OUT high time –...
Page 261 Device Specifications AC Characteristics for SAB 80C515-20 / 80C535-20 ± = 5 V 10 %; V = 0 V T = 0 °C to + 70 °C for port 0, ALE and PSEN outputs = 100 pF; C for all other outputs = 80 pF) Parameter Symbol Limit values...
Page 262 Device Specifications AC Characteristics (cont’d) Parameter Symbol Limit values Unit 20 MHz Variable clock clock = 3.5 MHz to 20 MHz CLCL min. max. min. max. External Data Memory Characteristics RD pulse width – – 100 – RLRH CLCL WR pulse width –...
Page 263 Device Specifications AC Characteristics (cont’d) Parameter Symbol Limit Values Unit Variable clock = 3.5 MHz to 20 MHz CLCL min. max. External Clock Drive Oscillator period CLCL High time – t CHCX CLCL CLCX Low time – t CLCX CLCL CHCX Rise time –...
Page 264 Device Specifications AC Characteristics (cont’d) Parameter Symbol Limit values Unit 20 MHz Variable clock clock = 3.5 MHz to 20 MHz CLCL min. max. min. max. System Clock Timing ALE to CLKOUT – – 40 – LLSH CLCL CLKOUT high time –...
Page 265 Device Specifications ROM Verification Characteristics ± ± = 25 °C 5 °C; V = 5 V 10 %; V = 0 V Parameter Symbol Limit values Unit min. max. ROM Verification Address to valid data 48 t – AVQV CLCL ENABLE to valid data 48 t –...
Page 266 Device Specifications Waveforms LHLL AVLL PLPH LLPL LLIV PLIV PSEN AZPL PXAV LLAX PXIZ PXIX Port 0 A0 - A7 Instr.IN A0 - A7 AVIV Port 2 A8 - A15 A8 - A15 MCT00096 Program Memory Read Cycle WHLH PSEN LLDV LLWL RLRH...
Page 267 Device Specifications WHLH PSEN LLWL WLWH QVWX AVLL WHQX LLAX2 QVWH A0 - A7 from A0 - A7 Instr.IN Port 0 Data OUT Ri or DPL from PCL AVWL Port 2 P2.0 - P2.7 or A8 - A15 from DPH A8 - A15 from PCH MCT00098 AC inputs during testing are driven at...
Page 268 Device Specifications AC Testing: Input, Output Waveforms AC Testing: Float Waveforms Semiconductor Group...
Page 269 Device Specifications Package Outlines Plastic Package, P-LCC-68 – SMD (Plastic Leaded Chip-Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Dimensions in mm Semiconductor Group...
Page 270 Device Specifications Package Outlines Plastic Package, P-MQFP-80 – SMD (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Dimensions in mm Semiconductor Group...

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