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Siemens SAK-C167CR-LM Manual

Microcontroller components.
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Stepping Code / Marking:
This Errata Sheet describes the deviations from the current user documentation. The
classification and numbering system is module oriented in a continual ascending sequence
over several derivatives, as well already solved deviations are included. So gaps inside this
enumeration could occur.
The current documentation is: Data Sheet: C167CR-4RM Data Sheet 07.97,
Note: Devices marked with EES- or ES are engineering samples which may not be
completely tested in all functional and electrical characteristics, therefore they should
be used for evaluation only.
The specific test conditions for EES and ES are documented in a separate Status Sheet.
Change summary to Errata Sheet Rel.1.0 for devices with stepping code/marking
ES-DB:
Modifications of ADM field while bit ADST = 0 (ADC.11)
P0H spikes after XPER write access and external 8-bit Non-multiplexed bus (X12)
ADC Overload Current (ADCC.2)
DC specification deviations added, limit for I
AC timing relaxations added, t5 (ALE high time) tested according to specification
Semiconductor Group
Errata Sheet
May 29, 1998 / Release 1.1
Device:
Package:
C167SR/CR-L25M Data Sheet Addendum 1998-03
User's Manual: C167 Derivatives User's Manual V2.0 03.96
Instruction Set Manual 12.97 Version 1.2
Errata Sheet, C167CR-LM, ES-DB, DB, 1.1, Mh
Microcontroller Components
SAK-C167CR-LM
SAK-C167CR-L25M
ES-DB, DB
MQFP-144
= –110 µA added
P0L
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   Summary of Contents for Siemens SAK-C167CR-LM

  • Page 1

    Microcontroller Components Errata Sheet May 29, 1998 / Release 1.1 Device: SAK-C167CR-LM SAK-C167CR-L25M Stepping Code / Marking: ES-DB, DB Package: MQFP-144 This Errata Sheet describes the deviations from the current user documentation. The classification and numbering system is module oriented in a continual ascending sequence over several derivatives, as well already solved deviations are included.

  • Page 2

    Functional Problems: PWRDN.1: Execution of PWRDN Instruction while pin NMI# = high When instruction PWRDN is executed while pin NMI# is at a high level, power down mode should not be entered, and the PWRDN instruction should be ignored. However, under the conditions described below, the PWRDN instruction may not be ignored, and no further instructions are fetched from external memory, i.e.

  • Page 3

    CPU.17: Arithmetic Overflow by DIVLU instruction For specific combinations of the values of the dividend (MDH,MDL) and divisor (Rn), the Overflow (V) flag in the PSW may not be set for unsigned divide operations, although an overflow occured. E.g.: MDH MDL F0F0 0F0Fh : F0F0h = FFFF FFFFh, but no Overflow indicated ! (result with 32-bit precision: 1 0000h)

  • Page 4

    ADC.11: Modifications of ADM field while bit ADST = 0 The A/D converter may unintentionally start one auto scan single conversion sequence when the following sequence of conditions is true: (1) the A/D converter has finished a fixed channel single or continuous conversion of an analog channel n >...

  • Page 5

    X12: P0H spikes after XPER write access and external 8-bit Non-multiplexed bus When an external 8-bit non-multiplexed bus mode is selected and P0H is used for general purpose I/O, and an internal (byte or word) write access to an XBUS peripheral (e.g. XRAM, CAN, or I²C module) is performed, and an external bus cycle is directly following the internal XBUS write cycle, then P0H is actively driven with the write data for approx.

  • Page 6

    Deviation from Electrical- and Timing Specification: The following table lists the deviations of the DC/AC characteristics from the specification in the C167CR-4RM Data Sheet 7.97 and C167SR/CR-L25M Data Sheet Addendum 1998-03 Problem Parameter Symbol Limit Values Unit Test min. max. short name Condition DCVOL.1...

  • Page 7

    Parameter Symbol Max CPU Clock Variable CPU Clock Unit = 20 1/2TCL = 1 to 20 MHz min. max. min. max. WR#/WRH# low time 38+tc 2TCL-12+tc (with RW-delay) instead of instead of 40+tc 2TCL -10+tc WR#/WRH# low time 63+tc 3TCL-12+tc (no RW-delay) instead of instead of...

  • Page 8

    ADCC.2: ADC Overload Current During exceptional conditions in the application system an overload current I can occur on the analog inputs of the A/D converter when V > V or V < V . For this case, the following conditions are specified in the Data Sheet: = | ±5 mA | OVmax...

  • Page 9

    6. Effects on the Conversion Result and TUE The effect on the conversion result and the TUE has to be calculated based on the current I the impedace of the analog source R causes an external voltage U∆n at the analog channel ASRC ANn which is the reason for an additional unadjusted error AUE of the conversion result.

  • Page 10

    History List (since device step BA) Functional Problems Functional Short Description Fixed in Problem step PWRDN.1 Execution of PWRDN Instruction while pin NMI# = high CPU.8 Jump instruction in EXTEND sequence CPU.9 PEC Transfers during instruction execution from Internal RAM CPU.11 Stack Underflow during Restart of Interrupted Multiply CPU.17...

  • Page 11

    In addition to the description in the C167 Derivatives User’s Manual V2.0, the following feature enhancements have been implemented in the C167CR-LM CB-step and all higher steps: Incremental position sensor interface For each of the GPT1 timers T2, T3, T4 of the GPT1 unit, an additional operating mode has been implemented which allows to interface to incremental position sensors (A, B, Top0).

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