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ALE
PSEN
WR
Port 0
Port 2
AC inputs during testing are driven at
Timing measurements are made at
Data Memory Write Cycle
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and
begins to float when a 100 mV deviation from the load voltage
Recommended Oscillator Circuits
Semiconductor Group
t
t
LLWL
WLWH
t
QVWX
t
AVLL
t
LLAX2
t
QVWH
A0 - A7 from
Data OUT
Ri or DPL
t
AVWL
P2.0 - P2.7 or A8 - A15 from DPH
V
C C – 0.5 V for a logic '1' and 0.45 V for a logic '0'.
V
I H min for a logic '1' and
*
267
Device Specifications
t
WHLH
t
WHQX
A0 - A7
Instr.IN
from PCL
A8 - A15 from PCH
V
I L max for a logic '0'.
V
/V
I
O L occurs.
O H
O L
MCT00098
/I
≥ ±
20 mA.
O H
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