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On-Chip Peripheral Components
7.3.1
Mode 0
Putting either timer/counter into mode 0 configures it as an 8-bit timer/counter with a divide-by-32
prescaler. Figure 7-21 shows the mode 0 operation.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1's
to all 0's, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an
interrupt (see section 8 for details about the interrupt structure).
The counted input is enabled to the timer when TR0 = 1 and either GATE = 0 or INT0 = 1 (setting
GATE = 1 allows the timer to be controlled by external input INT0, to facilitate pulse width
measurements). TR0 is a control bit in the special function register TCON; GATE is in TMOD.
The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL0. The upper 3 bits of TL0
are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers.
Mode 0 operation is the same for timer 0 as for timer 1. Substitute TR1, TF1, TH1, TL1, and INT1
for the corresponding timer 1 signals in figure 7-21. There are two different gate bits, one for timer 1
(TMOD.7) and one for timer 0 (TMOD.3).
*
Figure 7-21
Timer/Counter 0, Mode 0: 13 Bit-Timer/Counter
The same applies to timer/counter 1
Semiconductor Group
68
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