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If the power-down mode and the idle mode are set at the same time, power-down takes prece-
dence.
Furthermore, register PCON contains two general purpose flags. For example, the flag bits
GF0 and GF1 can be used to give an indication if an interrupt occurred during normal operation
or during an idle. Then an instruction that activates Idle can also set one or both flag bits. When
idle is terminated by an interrupt, the interrupt service routine can examine the flag bits.
The reset value of PCON is 000X0000
Table 4
SFR PCON (87
)
H
SMOD
PDS
7
6
Symbol
Position
SMOD
PCON.7
PDS
PCON.6
IDLS
PCON.5
–
PCON.4
GF1
PCON.3
GF0
PCON.2
PDE
PCON.1
IDLE
PCON.0
Idle Mode
In the idle mode the oscillator of the SAB 80C515 continues to run, but the CPU is gated off
from the clock signal. However, the interrupt system, the serial port, the A/D converter, and all
timers with the exception of the watchdog timer are further provided with the clock. The CPU
status is preserved in its entirety: the stack pointer, program counter, program status word,
accumulator, and all other registers maintain their data during idle mode.
The reduction of power consumption, which can be achieved by this feature depends on the
number of peripherals running.
Semiconductor Group
.
B
IDLS
–
5
4
Function
When set, the baud rate of the serial channel in mode 1, 2,
3 is doubled.
Power-down start bit. The instruction that sets the PDS flag
bit is the last instruction before entering the power-down
mode.
Idle start bit. The instruction that sets the IDLS flag bit is the
last instruction before entering the idle mode.
Reserved
General purpose flag
General purpose flag
Power-down enable bit. When set, starting of the power-
down mode is enabled.
Idle mode enable bit. When set, starting of the idle mode is
enabled.
GF1
GF0
3
2
*
244
Device Specifications
PDE
IDLE
1
0
87
H
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