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7.7
Watchdog Timer
As a means of graceful recovery from software or hardware upset a watchdog timer is provided in
the SAB 80(C)515/80(C)535. lf the software fails to clear the watchdog timer at least every
65532 µs, an internal hardware reset will be initiated. The software can be designed such that the
watchdog times out if the program does not progress properly. The watchdog will also time out if
the software error was due to hardware-related problems. This prevents the controller from
malfunctioning for longer than 65 ms if a 12-MHz oscillator is used.
The watchdog timer is a 16-bit counter which is incremented once every machine cycle. After an
external reset the watchdog timer is disabled and cleared to 0000 H . The counter is started by
setting bit SWDT (bit 6 in SFR IEN1). After having been started, the bit WDTS (watchdog timer
status, bit 6 in SFR IP0) is set. Note that the watchdog timer cannot be stopped by software. lt can
only be cleared to 0000 H by first setting bit WDT (IEN0.6) and with the next instruction setting
SWDT. Bit WDT will automatically be cleared during the second machine cycle after having been
set. For this reason, setting SWDT bit has to be a one cycle instruction (e.g. SETB SWDT). This
double instruction clearing of the watchdog timer was implemented to minimize the chance of
unintentionally clearing the watchdog. To prevent the watchdog from overflowing, it must be cleared
periodically.
Starting the watchdog timer by setting only bit SWDT does not reload the WDTREL register to the
watchdog timer registers WDTL/WDTH. A reload occurs only by using the double instruction refresh
sequence SETB WDT / SETB SWDT.
lf the software fails to clear the watchdog in time, an internally generated watchdog reset is entered
at the counter state FFFC H , which lasts four machine cycles. This internal reset differs from an
external reset only to the extent that the watchdog timer is not disabled. Bit WDTS (was set by
starting WDT) allows the software to examine from which source the reset was initiated. lf it is set,
the reset was caused by a watchdog timer overflow.
Figure 7-45
Special Function Register IEN0
0AF H
0A8 H
EAL
These bits are not used by the watchdog timer.
Bit
WDT
Semiconductor Group
0AE H
0AD H
0AC H
WDT
ET2
ES
Function
Watchdog timer refresh flag.
Set to initiate a refresh of the watchdog timer. Must be set directly before
SWDT is set to prevent an unintentional refresh of the watchdog timer.
WDT is reset by hardware two processor cycles after it has been set.
On-Chip Peripheral Components
*
0AB H
0AA H
0A9 H
ET1
EX1
ET0
105
0A8 H
EX0
IEN0
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