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Table 7-10
Status of External Pins During Idle and Power-Down Mode
Outputs
Last Instruction Executed from
Idle
ALE
High
PSEN
High
Port 0
Data
Port 1
Data/alternate
outputs
Port 2
Data
Port 3
Data/alternate
outputs
Port 4
Data
Port 5
Data
The watchdog timer is the only peripheral which is automatically stopped during idle. The idle mode
makes it possible to "freeze" the processor's status for a certain time or until an external event
causes the controller to go back into normal operating mode. Since the watchdog timer is stopped
during idle mode, this useful feature of the SAB 80C515/80C535 is provided even if the watchdog
function is used simultaneously.
lf the idle mode is to be used the pin PE must be held low. Entering the idle mode is to be done by
two consecutive instructions immediately following each other. The first instruction has to set the
flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5), the following instruction has to set the
start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). The hardware ensures that a
concurrent setting of both bits, IDLE and IDLS will not initiate the idle mode. Bits IDLE and IDLS will
automatically be cleared after having been set. lt one of these register bits is read the value shown
is zero (0). Figure 7-44 shows special function register PCON. This double-instruction sequence is
implemented to minimize the chance of unintentionally entering the idle mode.
Note that PCON is not a bit-addressable register, so the above mentioned sequence for entering
the idle mode is to be done by byte handling instructions.
Semiconductor Group
Internal Code Memory
Power-down
Low
Low
Data
Data/
last output
Data
Data/
last output
Data
Data
On-Chip Peripheral Components
Last Instruction Executed from
External Code Memory
Idle
High
High
Float
Data/alternate
outputs
Address
Data/alternate
outputs
Data
Data
*
103
Power-down
Low
Low
Float
Data/
last output
Data
Data/
last output
Data
Data
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