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On-Chip Peripheral Components
7.6.2.2 Idle Mode of the SAB 80C515/80C535
In idle mode the oscillator of the SAB 80C515/80C535 continues to run, but the CPU is gated off
from the clock signal. However, the interrupt system, the serial channel, the A/D converter and all
timers, except for the watchdog timer, are further provided with the clock. The CPU status is
preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and
all other registers maintain their data during idle mode.
The reduction of power consumption, which can be achieved by this feature, depends on the
number of peripherals running. lf all timers are stopped and the A/D converter and the serial
interface are not running, maximum power reduction can be achieved. This state is also the test
I
condition for the idle
(see the DC characteristics in the data sheet).
CC
Thus, the user has to make sure that the right peripheral continues to run or is stopped, respectively,
during idle. Also, the state of all port pins - either the pins controlled by their latches or controlled by
their secondary functions - depends on the status of the controller when entering idle.
Normally the port pins hold the logical state they had at the time idle was activated. lf some pins are
programmed to serve their alternate functions they still continue to output during idle if the assigned
function is on. This applies for the compare outputs as well as for the system clock output signal
and the serial interface in case the latter could not finish reception or transmission during normal
operation. The control signals ALE and PSEN are held at logic high levels (see table 7-10).
During idle, as in normal operating mode, the ports can be used as inputs. Thus, a capture or reload
operation as well as an A/D conversion can be triggered, the timers can be used to count external
*
events and external interrupts can be detected.
Semiconductor Group
102
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