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Figure 8-8
Priority-Within-Level Structure
High
Interrupt source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
Note:
This "priority-within-level" structure is only used to resolve simultaneous requests of the same
priority level.
8.3
How Interrupts are Handled
The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during
the following machine cycle. lf one of the flags was in a set condition at S5P2 of the preceding cycle,
the polling cycle will find it and the interrupt system will generate a LCALL to the appropriate service
routine, provided this hardware-generated LCALL is not blocked by any of the following conditions:
1)
An interrupt of equal or higher priority is already in progress.
2)
The current (polling) cycle is not in the final cycle of the instruction in progress.
3)
The instruction in progress is RETI or any write access to registers IEN0, IEN1, IEN2 or IP0
and IP1.
Any of these three conditions will block the generation of the LCALL to the interrupt service routine.
Condition 2 ensures that the instruction in progress is completed before vectoring to any service
routine. Condition 3 ensures that if the instruction in progress is RETI or any write access to
registers IEN0, IEN1 or IP0 and IP1, then at least one more instruction will be executed before any
interrupt is vectored too; this delay guarantees that changes of the interrupt status can be observed
by the CPU.
Semiconductor Group
→
Low
IADC
IEX2
IEX3
IEX4
IEX5
IEX6
Priority
High
↓
Low
*
122
Interrupt System
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