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Siemens SAB 80515 Series User Manual page 116

8-bit single-chip microcontroller family

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Figure 8-3
Special Function Register IEN1 (Address 0B8 H )
0BF H
0B8 H
EXEN2 SWDT
This bit is not used for interrupt control.
Bit
Function
EADC
Enables or disables the A/D converter interrupt.
If EADC = 0, the A/D converter interrupt is disabled.
EX2
Enables or disables external interrupt 2/capture/compare interrupt 4.
If EX2 = 0, external interrupt 2 is disabled.
EX3
Enables or disables external interrupt 3/capture/compare interrupt 0.
If EX3 = 0, external interrupt 3 is disabled.
EX4
Enables or disables external interrupt 4/capture/compare interrupt 0.
If EX4 = 0, external interrupt 4 is disabled.
EX5
Enables or disables external interrupt 5/capture/compare interrupt 0.
If EX5 = 0, external interrupt 5 is disabled.
EX6
Enables or disables external interrupt 6/capture/compare interrupt 0
If EX6 = 0, external interrupt 6 is disabled.
EXEN2
Enables or disables the timer 2 external reload interrupt.
EXEN2 = 0 disables the timer 2 external reload interrupt.
The external reload function is not affected by EXEN2.
In the following the interrupt sources are discussed individually.
The external interrupts 0 and 1 (INT0 and INT1) can each be either level-activated or negative
transition-activated, depending on bits IT0 and IT1 in register TCON (see figure 8-4). The flags that
actually generate these interrupts are bits IE0 and lE1 in TCON. When an external interrupt is
generated, the flag that generated this interrupt is cleared by the hardware when the service routine
is vectored too, but only if the interrupt was transition-activated. lf the interrupt was level-activated,
then the requesting external source directly controls the request flag, rather than the on-chip
hardware.
The timer 0 and timer 1 interrupts are generated by TF0 and TF1 in register TCON, which are set
by a rollover in their respective timer/counter registers (exception see section 7.3.4 for timer 0 in
mode 3). When a timer interrupt is generated, the flag that generated it is cleared by the on-chip
hardware when the service routine is vectored too.
Semiconductor Group
0BE H
0BD H
0BC H
EX6
EX5
0BB H
0BA H
0B9 H
EX4
EX3
*
116
Interrupt System
0B8 H
EX2
EADC
IEN1

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