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AC Characteristics (cont'd)
Parameter
External Data Memory Characteristics
RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD t
WR or RD high to ALE
high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD
Semiconductor Group
Symbol
20 MHz
clock
min.
max.
200
–
t
RLRH
200
–
t
WLWH
65
–
t
LLAX2
–
155
t
RLDV
t
0
–
RHDX
–
40
t
RHDZ
–
250
t
LLDV
*
t
–
285
AVDV
t
100
200
LLWL
70
–
AVWL
t
20
80
WHLH
5
–
t
QVWX
200
–
t
QVWH
10
–
t
WHQX
–
0
t
RLAZ
262
Device Specifications
Limit values
Variable clock
1/t
= 3.5 MHz to 20 MHz
CLCL
min.
6 t
– 100 –
CLCL
6 t
– 100 –
CLCL
2 t
– 35
–
CLCL
–
5 t
CLCL
0
–
–
2 t
CLCL
–
8 t
CLCL
–
9 t
CLCL
3 t
– 50
3 t
CLCL
CLCL
4 t
– 130 –
CLCL
t
– 30
t
CLCL
CLCL
– 45
–
t
CLCL
7 t
– 150 –
CLCL
– 40
–
t
CLCL
–
0
Unit
max.
ns
ns
ns
– 95
ns
ns
– 60
ns
– 150
ns
– 165
ns
+ 50
ns
ns
+ 30
ns
ns
ns
ns
ns
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