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Notes for page 249 and 250:
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be
superimposed on the V
capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0
transitions during bus operation.
In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may
exceed 0.8 V.
Then, it may be desirable to qualify ALE with a Schmitttrigger, or use an address latch
with a Schmitttrigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to
momentarily fall below the 0.9 V
3) Power-down I
CC
XTAL1 = N.C.; XTAL2 = V
4) I
(active mode) is measured with: XTAL2 driven with the clock signal according
CC
to the figure below; XTAL1 = N.C.; EA = Port 0 = Port 6 = V
pins are disconnected. I
5) I
(idle mode) is measured with: XTAL2 driven with the clock signal according to the
CC
figure below; XTAL1 = N.C.; EA = V
disconnected; all on-chip peripherals are disabled.
6) I
at other frequencies is given by:
CC
Active mode: I
CC max
Idle mode: I
CC max
where f
is the oscillator frequency in MHz.
OSC
is given in mA and measured at V
I
CC max
Semiconductor Group
of ALE and ports 1, 3, 4 and 5. The noise is due to external bus
OL
specification when the address bits are stabilizing.
CC
is measured with: EA = Port 0 = Port 6 = V
; RESET = V
SS
might be slightly higher if a crystal oscillator is used.
CC
SS
(mA) = 2.67 × f
(mA) = 0.88 × f
OSC
; V
= V
CC
AGND
SS
*
; Port 0 = Port 6 V
CC
(MHz) + 3.00
OSC
(MHz) + 2.50
= 5 V (see also notes 4 and 5)
CC
251
Device Specifications
;
CC
; all other pins are disconnected.
; RESET = V
; all other
CC
SS
; RESET = V
; all other pins are
CC
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