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On-Chip Peripheral Components
7.1.2
Port 0 and Port 2 Used as Address/Data Bus
As shown in figures 7-4 a) and 7-4 b), the output drivers of ports 0 and 2 can be switched to an
internal address or address/data bus for use in external memory accesses. In this application they
cannot be used as general purpose I/O, even if not all address lines are used externally. The
switching is done by an internal control signal dependent on the input level at the EA pin and/or the
contents of the program counter. lf the ports are configured as an address/data bus, the port latches
are disconnected from the driver circuit. During this time, the P2 SFR remains unchanged while the
P0 SFR has 1's written to it. Being an address/data bus, port 0 uses a pullup FET as shown in figure
7-4 a). When a 16-bit address is used, port 2 uses the additional strong pullups p1 to emit 1's for
the entire external memory cycle instead of the weak ones (p2 and p3) used during normal port
activity.
*
Figure 7-4 b)
Port 2 Circuitry
Semiconductor Group
41
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