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7.9
System Clock Output
For peripheral devices requiring a system clock, the SAB 80(C)515/80(C)535 provides a clock
output signal derived from the oscillator frequency as an alternate output function on pin P1.6/
CLKOUT. lf bit CLK is set (bit 6 of special function register ADCON, see figure 7-53), a clock signal
with 1/12 of the oscillator frequency is gated to pin P1.6/CLKOUT. To use this function the port pin
must be programmed to a one (1), which is also the default after reset.
Figure 7-53
Special Function Register ADCON (Address 0D8 H )
0DF H
0D8 H
BD
These bits are not used in controlling the clock out functions.
Bit
CLK
The system clock is high during S3P1 and S3P2 of every machine cycle and low during all other
states. Thus, the duty cycle of the clock signal is 1:6. Associated with a MOVX instruction the
system clock coincides with the last state (S3) in which a RD or WR signal is active. A timing
diagram of the system clock output is shown in figure 7-54.
Semiconductor Group
0DE H
0DD H 0DC H
CLK
–
BSY
Function
Clockout enable bit. When set, pin P1.6/CLKOUT outputs the system
clock which is 1/12 of the oscillator frequency.
On-Chip Peripheral Components
0DB H
0DA H
0D9 H
ADM
MX2
MX1
*
110
0D8 H
MX0
ADCON
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