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AC Characteristics (cont'd)
Parameter
External Data Memory Characteristics
RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
DATA hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
WR or RD high to ALE
high
Address valid to WR
Data valid to WR
transition
Data setup before WR
Data hold after WR
Address float after RD
Semiconductor Group
Symbol
12 MHz clock
min.
400
–
t
RLRH
400
–
t
WLWH
132
–
t
LLAX2
–
252
t
RLDV
0
–
t
RHDX
–
97
t
RHDZ
*
t
–
517
LLDV
t
–
585
AVDV
t
200
300
LLWL
t
43
123
WHLH
203
–
t
AVWL
33
–
t
QVWX
t
288
–
QVWH
t
13
–
WHQX
t
–
0
RLAZ
254
Device Specifications
Limit values
Variable clock
1/t
= 3.5 MHz to 12 MHz
CLCL
max.
min.
6 t
100
CLCL –
6 t
100
CLCL –
2 t
35
CLCL –
–
0
–
–
–
3 t
– 50
CLCL
t
– 40
CLCL
4 t
– 130
CLCL
– 50
t
CLCL
7 t
– 150
CLCL
t
– 50
CLCL
–
Unit
max.
–
ns
–
ns
–
ns
5 t
– 165
ns
CLCL
ns
2 t
– 70
ns
CLCL
8 t
– 150
ns
CLCL
9 t
– 165
ns
CLCL
3 t
+ 50
ns
CLCL
t
+ 40
ns
CLCL
–
ns
–
ns
–
ns
–
ns
0
ns
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