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Page 2 Figure 10-3 is removed. 10-4 to 10-5 10-3 to 10-4 Table 10-1; column P-SDIP-52 is removed. Chapter 11 The whole chapter is moved to the C541U Data Sheet. Edition 04.99 Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München...
Page 3 Critical components of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.
Page 4: Table Of Contents
General Information C541U Table of Contents Page Introduction ............1-1 Pin Configuration .
Page 5 General Information C541U Table of Contents Page 6.2.1.5 Mode 3 ............6-22 SSC Interface .
Page 6 General Information C541U Table of Contents Page Interrupt System ..........7-1 Interrupt Registers .
Page 8: Introduction
Introduction C541U Introduction The C541U is a member of the Siemens C500 family of 8-bit microcontrollers They are fully compatible to the standard 80C51 architecture. The C541U especially provides an on-chip USB module compliant to the USB specification, which is capable to operate either in low or full speed mode. The five endpoints can be easily controlled by the CPU via special function registers.
Page 9 Introduction C541U Listed below is a summary of the main features of the C541U : • Enhanced 8-bit C500 CPU – Full software/toolset compatible to standard 80C51/80C52 microcontrollers • 12 MHz external operating frequency – 500 ns instruction cycle •...
Page 10 Introduction C541U XTAL2 XTAL1 Port 0 8-bit Digital I/O Port 1 6-bit Digital I/O PSEN C541U Port 2 RESET 8-bit Digital I/O Port 3 8-bit Digital I/O Figure 1-2 Logic Symbol Semiconductor Group 1997-10-01...
Page 11: Pin Configuration
Introduction C541U Pin Configuration This section describes the pin configurations of the C541U in the P-LCC-44 package. 44 43 42 41 40 P1.2/SCLK P0.4/AD4 P0.5/AD5 P0.6/AD6 RESET P0.7/AD7 P3.0/LED2 C541U P1.4/STO P1.3/SRI P3.1/DADD P3.2/INT0 PSEN P3.3/INT1 P2.7/A15 P3.4/T0 P2.6/A14 P3.5/T1 P2.5/A13...
Page 12: Pin Definitions And Functions
Introduction C541U Pin Definitions and Functions This section describes all external signals of the C541U with its function. Table 1-1 Pin Definitions and Functions Symbol I/O*) Function Numbers P-LCC-44 USB D+ Data Line The pin D+ can be directly connected to USB cable (transceiver is integrated on-chip).
Page 13 Introduction C541U Table 1-1 Pin Definitions and Functions (cont’d) Symbol I/O*) Function Numbers P-LCC-44 P3.0 - P3.7 11, 13 - 19 Port 3 is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1’s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs.
Page 14 When held high, the C541U executes instructions from the internal OTP program memory as long as the PC is less than 2000 H for the C541U. When held low, the C541U fetches all instructions from external program memory. For the C541U-L this pin must be tied low.
Page 15 Introduction C541U Table 1-1 Pin Definitions and Functions (cont’d) Symbol I/O*) Function Numbers P-LCC-44 ECAP – External Capacitor This pin is required to be connected to an external capacitor which is connected to . The value of the capacitor is 6 nF.
Page 16: Fundamental Structure
C541U Fundamental Structure The C541U is fully compatible to the architecture of the standard 8051/C501 microcontroller family. While maintaining the typical architectural characteristics of the C501, the C541U incorporates a SSC synchronous serial interface, a versatile USB module as well as some enhancements in the Fail Save Mechanism Unit.
Page 17: Cpu
44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz clock, 58% of the instructions execute in 500 ns. The CPU (Central Processing Unit) of the C541U consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder.
Page 18 Fundamental Structure C541U Special Function Register PSW (Address D0 H ) Reset Value : 00 H Bit No. MSB D7 H D6 H D5 H D4 H D3 H D2 H D1 H D0 H D0 H Function Carry Flag Used by arithmetic instruction.
Page 19: Cpu Timing
C541U CPU Timing The C541U has no clock prescaler. Therefore, a machine cycle of the C541U consists of 6 states (6 oscillator periods). Each state is devided into a phase 1 half and a phase 2 half. Thus, a machine cycle consists of 6 oscillator periods, numbererd S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2).
Page 20 Fundamental Structure C541U P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 (XTAL2) Read Read Next Read Next Opcode Opcode (Discard) Opcode Again (a) 1-Byte, 1-Cycle Instruction, e. g. INC A...
Page 21 Fundamental Structure C541U Semiconductor Group 1997-10-01...
Page 22: Memory Organization
Memory Organization C541U Memory Organization The C541U CPU manipulates operands in the following four address spaces: – 8 KByte on-chip OTP program memory – Totally up to 64 Kbyte internal/external program memory – up to 64 Kbyte of external data memory –...
Page 23: Program Memory, "Code Space
The C541U has 8 Kbyte of OTP program memory which can be externally expanded up to 64 Kbytes. If the EA pin is held high, the C541U executes program code out of the internal OTP program memory unless the program counter address exceeds 1FFF H . Address locations 2000 H through FFFF H are then fetched from the external program memory.
Page 24 The 75 special function registers (SFRs) in the SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C541U are listed in table 3-1 and table 3-2. In table 3-1 they are organized in groups which refer to the functional blocks of the C541U.
Page 25 1) Bit-addressable special function registers 2) “X“ means that the value is undefined and the location is reserved 3) The content of this SFR varies with the actual of the step C541U (eg. 01 for the first step) 4) This SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Page 26 Memory Organization C541U Table 3-1 Special Function Registers - Functional Blocks (cont’d) Block Symbol Name Address Contents after Reset Pow. Sav. PCON Power Control Register 87 H X00X0000 B Modes PCON1 Power Control Register 1 88 H 0XX0XXXX B EPSEL...
Page 27 Memory Organization C541U Table 3-2 Contents of the SFRs, SFRs in numeric order of their addresses Addr Register Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value 80 H FF H...
Page 28 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers 5) The content of this SFR varies with the actual step of the C541U (e.g. 01 for the first step) 6) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset 7) These registers are only used in USB low-speed operation.
Page 29 3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set. 4) These are read-only registers 5) The content of this SFR varies with the actual step of the C541U (e.g. 01 for the first step) 6) The reset value of ADROFF is valid only if USBVAL has not been read or written since the last hardware reset.
Page 30 Memory Organization C541U Table 3-3 Contents of the USB Device and Endpoint Registers (Addr. C1 H to C7 H ) Addr Register Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value EPSEL = 1XXX.XXXX B Device Registers...
Page 31 Memory Organization C541U Table 3-3 Contents of the USB Device and Endpoint Registers (Addr. C1 H to C7 H ) (cont’d) Addr Register Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value EPSEL = 0XXX.X010 B...
Page 32: External Bus Interface
External Bus Interface C541U External Bus Interface The C541U allows for external memory expansion. The functionality and implementation of the external bus interface is identical to the common interface for the 8051 architecture. Accessing External Memory It is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively.
Page 33 External Bus Interface C541U One Machine Cycle One Machine Cycle PSEN without MOVX INST. INST. INST. INST. INST. PCL OUT PCL OUT PCL OUT PCL OUT valid valid valid valid One Machine Cycle One Machine Cycle PSEN with MOVX DPH OUT OR P2 OUT INST.
Page 34: Timing
In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the C541U the external program and data memory spaces can be combined by the logical-AND of PSEN and RD. A positive result from this AND operation produces a low active read strobe that can be used for the combined physical memory.
Page 35: Ale, Address Latch Enable
The C541U allows to switch off the ALE output signal. If the internal OTP program memory is used (EA=1) and ALE is switched off by EALE=0, ALE will only go active during external data memory accesses (MOVX instructions) and code memory accesses with an address greater than 1FFF H for the C541U (external code memory fetches).
Page 36: Enhanced Hooks Emulation Concept
Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU. “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens. Semiconductor Group 1997-10-01...
Page 37 External Bus Interface C541U Semiconductor Group 1997-10-01...
Page 38: Reset And System Clock Operation
Reset and System Clock Operation Hardware Reset Operation The hardware reset function incorporated in the C541U allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power down mode is to be terminated.
Page 39 (or high). The content of the internal RAM of the C541U is not affected by a reset. After power-up the content is undefined, while it remains unchanged during a reset if the power supply is not turned off.
Page 40: Fast Internal Reset After Power-On
In the C541U the oscillator watchdog unit avoids this situation. In this case, after power-on the oscillator watchdog’s RC oscillator starts working within a very short start-up time (typ. less than 2 microseconds).
Page 41 Reset / System Clock C541U Figure 5-2 Power-On Reset of the C541U Semiconductor Group 1997-10-01...
Page 42: Hardware Reset Timing
XTAL1 and XTAL2 pins). The RESET signal must be active for at least two machine cycles; after this time the C541U remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle.
Page 43: Oscillator And Clock Circuit
Block Diagram of the Clock Generation Circuitry In low speed mode the PLL is not required. Therefore, the PLL should be always disabled in low speed mode. This also reduces the power consumption and the EMC of the C541U when used in low speed mode.
Page 44 Reset / System Clock C541U After a hardware reset operation bits PCLK, SPEED, and UCLK are set to 0. Depending on the required operating mode of the USB module a well defined procedure must be executed for switching on the clock for the USB module : –...
Page 45 Figure 5-6 On-Chip Oscillator Circuiry To drive the C541U with an external clock source, the external clock signal has to be applied to XTAL1, as shown in figure 5-7. XTAL2 has to be left unconnected. A pullup resistor is suggested...
Page 46: On-Chip Peripheral Components
7. Parallel I/O The C541U three 8-bit I/O ports and one 6-bit I/O port (Port 1). Port 0 is an open-drain bidirectional I/O port, while ports 1 to 3 are quasi-bidirectional I/O ports with internal pullup resistors. That means, when configured as inputs, ports 1 to 3 will be pulled high and will source current when externally pulled low.
Page 47: Port Structures
6.1.1 Port Structures The C541U allows for digital I/O on 30 lines grouped into 4 bidirectional 8-/6-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P3 are performed via their corresponding special function registers P0 to P3.
Page 48: Basic Port Circuirty Of Port 1 To 3
On-Chip Peripheral Components C541U 6.1.1.1 Basic Port Circuirty of Port 1 to 3 Port 1, 2 and 3 output drivers have internal pullup FET’s (see figure 6-2). Each I/O line can be used independently as an input or output. To be used as an input, the port bit stored in the bit latch must contain a one (1) (that means for figure 6-2: Q=0), which turns off the output driver FET n1.
Page 49 On-Chip Peripheral Components C541U In fact, the pullups mentioned before and included in figure 6-2 are pullup arrangements as shown in figure 6-3. One n-channel pulldown FET and three pullup FETs are used: Delay = 1 State < Port Input Data...
Page 50 On-Chip Peripheral Components C541U The described activating and deactivating of the four different transistors results in four states which can be : – input low state (IL), p2 active only – input high state (IH) = steady output high state (SOH), p2 and p3 active –...
Page 51: Ssc Port Pins Of Port 1
On-Chip Peripheral Components C541U 6.1.1.2 SSC Port Pins of Port 1 The port pins of the SSC interface are located as alternate functions at four lines of port 4 : – P1.2/SCLK : when used as SSC clock output, pin becomes a true push-pull output –...
Page 52 On-Chip Peripheral Components C541U Delay = 1 State 1 < 1 < Port & 1 < Tristate Input Data (Read Pin) MCS02433 Figure 6-5 Driver Circuit of Port 1 pins P1.3 and P1.5 (when used for SRI and SLS) When enabling the SSC, inputs used for the SSC will be switched into a high-impedance mode. For P1.3/SRI, Tristate will be enabled, when the SSC is enabled.
Page 53: Port 0 Circuitry
On-Chip Peripheral Components C541U 6.1.1.3 Port 0 Circuitry Port 0, in contrast to ports 1, 2 and 3, is considered as "true" bidirectional, because the port 0 pins float when configured as inputs. Thus, this port differs in not having internal pullups. The pullup FET in the P0 output driver (see figure 6-6) is used only when the port is emitting 1 s during the external memory accesses.
Page 54: Port 0 And Port 2 Used As Address/Data Bus
On-Chip Peripheral Components C541U 6.1.1.4 Port 0 and Port 2 used as Address/Data Bus As shown in figure 6-6 and below in figure 6-7, the output drivers of ports 0 and 2 can be switched to an internal address or address/data bus for use in external memory accesses. In this application they cannot be used as general purpose I/O, even if not all address lines are used externally.
Page 55: Alternate Functions
On-Chip Peripheral Components C541U 6.1.2 Alternate Functions The pins of ports 1 and 3 are multifunctional. They are port pins and also serve to implement special features as listed in table 6-1. Figure 6-8 shows a functional diagram of a port latch with alternate function. To pass the alternate function to the output pin and vice versa, however, the gate between the latch and driver circuit must be open.
Page 56 On-Chip Peripheral Components C541U Ports 1 and 3 are provided for several alternate functions, as listed in table 6-1: Table 6-1 Alternate Functions of Port 1 and 3 Port Alternate Function P1.0 Input to counter 2 P1.1 T2EX Capture-reload trigger of timer 2 / up down count P1.2...
Page 57: Port Handling
On-Chip Peripheral Components C541U 6.1.3 Port Handling 6.1.3.1 Port Timing When executing an instruction that changes the value of a port latch, the new value arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches are only sampled by their output buffers during phase 1 of any clock period (during phase 2 the output buffer holds the value it noticed during the previous phase 1).
Page 58: Port Loading And Interfacing
The output buffers of ports 1, 2 and 3 can drive TTL inputs directly. The maximum port load which still guarantees correct logic output levels can be looked up in the C541U DC characteristics in chapter 10. The corresponding parameters are The same applies to port 0 output buffers.
Page 59: Read-Modify-Write Feature Of Ports 1,2 And 3
On-Chip Peripheral Components C541U 6.1.3.3 Read-Modify-Write Feature of Ports 1,2 and 3 Some port-reading instructions read the latch and others read the pin. The instructions reading the latch rather than the pin read a value, possibly change it, and then rewrite it to the latch. These are called "read-modify-write"- instructions, which are listed in table 6-2.
Page 60: Timers/Counters
6.2.1 Timer/Counter 0 and 1 Timer / counter 0 and 1 of the C541U are fully compatible with timer / counter 0 and 1 of the 80C51/ C501 and can be used in the same four operating modes: Mode 0: 8-bit timer/counter with a divide-by-32 prescaler...
Page 61 On-Chip Peripheral Components C541U 6.2.1.1 Timer/Counter 0 and 1 Registers Totally six special function registers control the timer/counter 0 and 1 operation : – TL0/TH0 and TL1/TH1 - counter registers, low and high part – TCON and TMOD - control and mode select registers...
Page 62 On-Chip Peripheral Components C541U Special Function Register TCON (Address 88 H ) Reset Value : 00 H Bit No. 8F H 8E H 8D H 8C H 8B H 8A H 89 H 88 H 88 H TCON The shaded bits are not used for controlling timer/counter 0 and 1.
Page 63 On-Chip Peripheral Components C541U Special Function Register TMOD (Address 89 H ) Reset Value : 00 H Bit No. 89 H Gate Gate TMOD Timer 1 Control Timer 0 Control Function GATE Timer 1/0 gating control When set, timer/counter "x" is enabled only while "INT x" pin is high and "TRx"...
Page 64: Mode 0
On-Chip Peripheral Components C541U 6.2.1.2 Mode 0 Putting either timer/counter 0,1 into mode 0 configures it as an 8-bit timer/counter with a divide-by- 32 prescaler. Figure 6-10 shows the mode 0 operation. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0.
Page 65 On-Chip Peripheral Components C541U 6.2.1.3 Mode 1 Mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in figure 6-11. Figure 6-11 Timer/Counter 0, Mode 1: 16-Bit Timer/Counter...
Page 66 On-Chip Peripheral Components C541U 6.2.1.4 Mode 2 Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in figure 6-12. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software.
Page 67 On-Chip Peripheral Components C541U 6.2.1.5 Mode 3 Mode 3 has different effects on timer 0 and timer 1. Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1=0. Timer 0 in mode 3 establishes TL0 and TH0 as two seperate counters.
Page 68: Ssc Interface
C541U SSC Interface The C541U microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. It can be used for simple I/O expansion via shift registers, for connection of a variety of peripheral components, such as A/D converters, EEPROMs etc., or for allowing several microcontrollers to be interconnected in a master/slave structure.
Page 69: General Operation Of The Ssc
On-Chip Peripheral Components C541U As the SSC is a synchronous serial interface, for each transfer a dedicated clock signal sequence must be provided. The SSC has implemented a clock control circuit, which can generate the clock via a baud rate generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is fully programmable for clock polarity and phase.
Page 70: Baudrate Generation (Master Mode Only)
On-Chip Peripheral Components C541U When the SSC is enabled and in master mode, pins P1.3 / SRI, P1.4 / STO, and P1.2 / SCLK will be switched to the SSC control function. P1.4 / STO and P1.2 / SCLK actively will drive the lines P1.5 / SLS will remain a regular I/O pin.
Page 71: Master/Slave Mode Selection
On-Chip Peripheral Components C541U 6.3.5 Master/Slave Mode Selection The selection whether the SSC operates in master mode or in slave mode has to be made depending on the hardware configuration before the SSC will be enabled. Normally a specific device will operate either as master or as slave unit. The SSC has no on-chip support for multimaster configurations (switching between master and slave mode operation).
Page 72: Data/Clock Timing Relationships
On-Chip Peripheral Components C541U 6.3.6 Data/Clock Timing Relationships The SSC provides four different clocking schemes for clocking the data in and out of the shift register. Controlled by two bits in SSCCON, the clock polarity (idle state of the clock, control register bit CPOL) and the clock/data relationship (phase control, control register bit CPHA), i.e.
Page 73: Slave Mode Operation
On-Chip Peripheral Components C541U 6.3.6.2 Slave Mode Operation Figure 6-17 shows the clock/data/control relationship of the SSC in slave mode. When SLS is active (low) and CPHA is 1, the MSB (or LSB) of the data that was written into the shift register will be provided on the transmitter output after the first clock edge (if the transmitter was enabled by setting the TEN bit to 1), the receiver input will sample the input data with the next clock edge.
Page 74: Register Description
On-Chip Peripheral Components C541U 6.3.7 Register Description The SSC interface has six SFRs which are listed in table 6-3. Table 6-3 Special Function Registers of the COMP Unit Symbol Description Address SSCCON SSC Control Register 93 H SCIEN SSC Interrupt Enable Register...
Page 75 On-Chip Peripheral Components C541U Function CPOL Clock polarity This bit controls the polarity of the shift clock and in conjunction with the CPHA bit which clock edges are used for sample and shift. CPOL=0 : SCLK idle state is low.
Page 76 On-Chip Peripheral Components C541U This register enables or disables interrupt request for the status bits. SCIEN must only be written when the SSC interrupts are disabled in the general interrupt enable register IEN2 (9A H ) using bit ESSC otherwise unexpected interrupt requests may occur.
Page 77 On-Chip Peripheral Components C541U Special Function Register SCF (Address AB H ) Reset Value : XXXXXX00 B Bit No. AB H – – – – – – WCOL Function – Reserved for future use. WCOL SSC write collision detect If WCOL is set it indicates that an attempt was made to write to the shift register STB while a data transfer was in progress and not fully completed.
Page 78 After reset the contents of the shift register and the receive buffer register are undefined. The register SSCMOD is used to enable test modes during factory test. It must not be written or modified during normal operation of the C541U. Special Function Register SSCMOD (Address 96 H ) Reset Value : 00 H Bit No.
Page 79: Usb Module
C541U USB Module The USB module in the C541U handles all transactions between the serial USB bus and the internal (parallel) bus of the microcontroller. The USB module includes several units which are required to support data handling with the USB bus : the on-chip USB bus transceiver, the USB memory with...
Page 80: Transfer Modes
Isochronous data transfer has the highest priority, but is not always lossless. Isochronous pipes are always unidirectional, so one endpoint can be associated to an IN pipe or an OUT pipe. The C541U supports up to 64 bytes. Interrupt Interrupt data are a small amount of data, which are transferred to the host every n frames, with n being programmable by the host.
Page 81: Usb Memory Buffer Modes
6.4.2.1 Overview Every endpoint of the USB module in the C541U can operate in two modes, dual buffer mode and single buffer mode. Each mode provides random or sequential access to the USB memory. Figure 6-19 shows the possible buffer modes.
Page 82: Usb Write Access
On-Chip Peripheral Components C541U 6.4.2.2 Single Buffer Mode In single buffer mode the USB and the CPU share one common USB memory page. The active buffer page can be either page 0 or page 1. Back-to-back transfers are not possible in this mode.
Page 83 On-Chip Peripheral Components C541U Figure 6-21 shows more details of an USB write access to USB memory in single buffer mode. After SOF(n) (start of frame) occured at , the USB starts writing at a fixed number of bytes into the USB memory.
Page 84: Usb Read Access
On-Chip Peripheral Components C541U 6.4.2.2.2 USB Read Access Figure 6-22 shows the basic flowchart of a USB read access from one USB memory buffer in single buffer mode. Buffer is empty: USB read access disabled CPU write access enabled Buffer can be written by CPU...
Page 85 On-Chip Peripheral Components C541U The standard USB read access as shown in figure 6-23 supports random and sequential CPU access mode of the USB memory. The memory buffer full condition is true when a predefined number of bytes (MaxLen) has been written by the CPU or when bit DONE has been set by software.
Page 86 On-Chip Peripheral Components C541U The start-of-frame-done enable feature (SOFDE=1) is useful for USB memory read accesses when the number of data bytes to be transferred from CPU to USB is not predictable (see figure 6-24). The CPU can write data as desired to USB memory until a SOF occures (every 1 ms). The automatic setting of bit SOF causes bit EOD to be set (at ).
Page 87: Dual Buffer Mode
On-Chip Peripheral Components C541U 6.4.2.3 Dual Buffer Mode In dual buffer mode, both USB memory pages (page 0 and page 1) are used for data transfers. The logical assignment of the memory pages to CPU or USB is automatically switched. The following two figures show the buffer handling concept in dual buffer mode for the USB read access and USB write access.
Page 88 On-Chip Peripheral Components C541U CPU Buffer Handling USB Buffer Handling CPU page is full : CBF = 1 USB page is empty : UBF = 0 CPU read access enabled USB write access enabled CPU reads 1 Byte USB write...
Page 89 On-Chip Peripheral Components C541U Figure 6-27 describes an example of a USB read operation in sequential mode with both buffers empty at the beginning of the USB read operation. The CPU starts writing data with sequential access (INCE=1) to the buffer assigned to the CPU at .
Page 90 On-Chip Peripheral Components C541U Another way to initiate buffer switching is setting bit DONE by software. This feature, which is shown in figure 6-28 for USB read access, can be used to transfer a variable number of bytes. The maximum number of bytes to be transferred is still determined by MaxLen, which is not changed when bit DONE is set.
Page 91 On-Chip Peripheral Components C541U If bit SOFDE is set, buffer switching is done automatically after SOF (start of frame) has been detected by the USB. Figure 6-29 describes this functionality for USB read access for this case. The buffer which contains the latest data from the CPU is tagged valid for USB access (UBF=1) at and the buffers are swapped if the USB buffer is empty.
Page 92 On-Chip Peripheral Components C541U If the number of data bytes to be transferred is greater than the maximum packet size (given by MaxLen), the data is split up automatically into packets, which are transferred one after the other. Figure 6-30 gives an example of an USB read access, where data from the CPU is split up into two packets.
Page 93 On-Chip Peripheral Components C541U In general, three criteria for buffer switching are implemented in the USB module : a) For sequential access, the address offset register ADROFF is automatically incremented after each read or write action of the CPU. The address offset value (before incrementing) represents the number of bytes stored in USB memory for a specific endpoint.
Page 94: Usb Memory Buffer Organization
On-Chip Peripheral Components C541U 6.4.3 USB Memory Buffer Organization The address generation of the USB memory buffer is based on address offset and base address pointer. This scheme allows flexible and application specific buffer allocation and management. The length of an endpoint buffer can be up to 8, 16, 32, or 64 bytes. The start address of each endpoint buffer can be located to memory locations according table 6-5.
Page 95: Usb Memory Buffer Address Generation
On-Chip Peripheral Components C541U 6.4.4 USB Memory Buffer Address Generation The generation of an USB memory address for USB access (read or write) depends on the EPNum (endpoint number) information, which has been transmitted to the USB module during the software initialization procedure.
Page 96: Initialization Of Usb Module
On-Chip Peripheral Components C541U 6.4.5 Initialization of USB Module After a hardware reset operation bits PCLK, SPEED, and UCLK are set to 0. If full speed operation is required, a well defined procedure must be executed for switching on the clock for the USB module : –...
Page 97 On-Chip Peripheral Components C541U Table 6-6 Bitfield Definition of USB Configuration Block Bitfield Description EPNum This 3-bit field specifies the number of the endpoint (0-4) for which the actual configuration byte block is valid. This 3-bit field must be referenced in byte 0 and byte 3 of a configuration byte block.
Page 98: Control Transfer
(bit SUI is set) indicates the end of a setup phase. Additionally, the status and control bits UBF, CBF and SOD are reset. Since C541U only supports single device configuration and single interface, setting multiple device configuration through “set_configuration” and setting alternate interface through “set_interface” to the device will be ignored.
Page 99: Register Set
USB module and can be accessed via unique SFR addresses. For reduction of the number of SFR addresses which are needed to control the USB module inside the C541U, device registers and endpoint registers are mapped into an SFR address block of seven SFR addresses (C1 H to C7 H ).
Page 100 On-Chip Peripheral Components C541U 6.4.7.1 Global Registers The global registers GEPIR, EPSEL, ADROFF, and USBVAL describe the global functionality of the USB module and can be accessed via unique SFR addresses. The Endpoint Select Register EPSEL contains 4 bits which are used to select one of the register blocks of the five endpoint register blocks or the device register block.
Page 101 On-Chip Peripheral Components C541U Table 6-7 Endpoint/Device Register Set Address Assignment EPSEL SFR Addr. Selected Register 1XXXXXXX B C1 H : Device Control Register C2 H DPWDR: Device Power Down Register C3 H DIER : Device Interrupt Enable Register (Device register...
Page 102 On-Chip Peripheral Components C541U In most cases the CPU accesses only one endpoint buffer until it is full (CBF=1 at CPU write access) or empty (CBF=0 at CPU read access). As the USB memory size is 128 bytes per page, the maximum packet length is limited to 64 bytes.
Page 103 On-Chip Peripheral Components C541U The global endpoint interrupt request register GEPIRn (n=0-4) contaíns one flag for each endpoint which indicates whether one or more of the eight endpoint specific interrupt requests have become active. If a request flag in GEPIR is set, it is automatically cleared after a read operation of the corresponding endpoint specific EPIRn register.
Page 104: Device Registers
SPEED Low / full speed select Bit SPEED configures the USB module in the C541U for full speed (12 MBaud) or low speed (1.5 MBaud) mode. This bit can only be written with bit SWR=1 (software reset). After hardware reset the USB module runs in low speed mode and the PLLx4 is automatically disabled.
Page 105: Low Speed Mode
On-Chip Peripheral Components C541U Function DINIT Device initialization in progress At the end of a software reset, bit DINIT is set by hardware. After software reset of the USB module, the USB module must be initialized by the CPU. When DINIT is set after a software reset, 5 bytes for each endpoint must be written to SFR USBVAL.
Page 106 RPWD must be cleared by software to enable again data reception. If RPWD is set, the USB bus cannot wake-up the C541U form power down mode. If RPWD=0, the USB receiver is active (default after reset).
Page 107 On-Chip Peripheral Components C541U The device interrupt enable register DIER contains the enable bits for the different types of device interrupts. With these bits, the device interrupts can be individually enabled or disabled. The general device interrupt enable bit EUDI is located in SFR IEN1. A device interrupt can be only generated if EUDI and EA (global interrupt enable bit in IEN0) are set too.
Page 108 On-Chip Peripheral Components C541U Function SUIE Setup interrupt enable Bit SUIE enables the generation of a device interrupt on a succesful reception of a setup packet which must be processed by the CPU. If SUIE=0, the setup interrupt is disabled.
Page 109 On-Chip Peripheral Components C541U The device interrupt request register DIRR contains the interrupt request flags of the different types of device interrupts. All Interrupt request flags in DIRR are reset by hardware after DIRR has been read. USB Device Interrupt Request Register DIRR (Address C4 H ) Reset Value : 00 H Bit No.
Page 110 On-Chip Peripheral Components C541U The frame number registers stores an 11-bit value which defines the number of an USB frame. The frame number rolls over upon reaching its maximum value of 7FF . The FNRH/FNRL registers are read only registers which are reset to 00 H by a hardware reset.
Page 111 On-Chip Peripheral Components C541U 6.4.7.3 Endpoint Registers Each of the five endpoints has its own endpoint register set which contains the following registers (n=0-4) : – EPBCn Endpoint n Buffer Control Register – EPBSn Endpoint n Buffer Status Register – EPIERn Endpoint n Interrupt Enable Register –...
Page 112 On-Chip Peripheral Components C541U Function INCEn Auto increment enable If bit INCE is set, the address offset register ADROFF for CPU access to USB memory is automatically incremented after each data write or data read action of the USBVAL register. This allows the user to handle the USB memory like a FIFO without modification of the address of the desired memory location by software.
Page 113 On-Chip Peripheral Components C541U The bits of the endpoint buffer status registers indicate the status of the endpoint specific USB memory buffers and allows setting of certain USB memory buffer conditions. Endpoint Buffer Status Register EPBSn, n=0-4 (Address C2 H ) Reset Value : 20 H Bit No.
Page 114 On-Chip Peripheral Components C541U Function SETWRn Set direction of USB memory buffer to write Bit SETWRn is used to predict the direction of the next USB access for endpoint n as an USB write access. A faulty prediction causes no errors since the USB module determines the real direction.
Page 115 On-Chip Peripheral Components C541U The endpoint interrupt enable registers contain the endpoint specific interrupt enable bits. With these bits, the endpoint specific interrupts can be individually enabled or disabled. Additionally to a bit in an EPIEn register, the global interrupt bit EPIn in GEPIR for endpoint n and the general endpoint interrupt bit EUEI in IEN1 and the general interrupt enable bit EA in IEN0 must be set for the interrupt becoming active.
Page 116 On-Chip Peripheral Components C541U Function EODIEn End of data interrupt enable Bit EODIEn enables the generation of an endpoint specific end of data interrupt when bit EODn in register EPIRn is set. If EODIEn=0, the end of data interrupt is disabled.
Page 117 On-Chip Peripheral Components C541U The endpoint interrupt request register EPIRn contains the interrupt request flags of the different endpoint specific interrupts. In general, the bits in EPIRn are reset by hardware after a EPIRn read operation. Endpoint Interrupt Request Register EPIRn, n=0-4 (Address C4 H ) Reset Value EPIR0 : 11 H Reset Value EPIR1 to EPIR4 : 10 H Bit No.
Page 118 On-Chip Peripheral Components C541U Function SODn Start of data USB Read action: SODn is set if the USB has read a fixed number (USBLen) of bytes from the transmit buffer. As a result, the buffer is empty now and the CPU can process write actions again.
Page 119 On-Chip Peripheral Components C541U The endpoint base address register defines the location and size (start address and length) of the endpoint specific buffers in the USB memory. See also figure 6-31 for an example of EPBAn and EPLENn register setup.
Page 120: Initialization
On-Chip Peripheral Components C541U 6.4.8 Low Speed Mode The features of this mode are listed below : • Data rate of 1.5 Mbit/s • Three endpoints : one bidirectional control endpoint, EP0 two interrupt endpoints, EP1 and EP2 • Maximum data packet length of 8 bytes, fully direct accesible data packet •...
Page 121: Transfer Modes
USBDCR register. The stage is completed by writing ‘Empty’ to the TYPE bit field. Since C541U only supports single device configuration and single interface, setting multiple device configuration through “set_configuration” and setting alternate interface through “set_interface” to the device will be ignored.
Page 122: Interrupt Transfer
On-Chip Peripheral Components C541U 6.4.8.4 Interrupt Transfer The direction of this transfer is always from the device to the host. The usage is intended for device polling with programmable rate from 10 ms to 255 ms. A no acknowledge handshake (NACK) is automatically returned to the host, if the device has currently no interrupt data to transfer.
Page 123: Register Set
On-Chip Peripheral Components C541U 6.4.8.5 Register Set A set of control and data registers are defined for the USB module in low speed operation. USB Module Control Register USBDCR (Address E7 H ) Reset Value : 00 H Bit No.
Page 124 On-Chip Peripheral Components C541U Function TYPE3 - 0 Transfer Type TYPE3 - 0 Description 0110 Interrupt 1 Software is required to write this value for the host to read the data associated with EP1interrupt endpoint from the USBDRn registers. 0111...
Page 125 On-Chip Peripheral Components C541U Function LEN3 - 0 Length Information contains the number of bytes currently stored in the USB data registers. LEN is set to 1111 when the hardware accesing the USBDRn registers. Bitfield LEN is updated either by USB or by CPU.
Page 126 On-Chip Peripheral Components C541U USB Module Power Down Register USBPWD (Address E6 H ) Reset Value : 00 H Bit No. E6 H USBPWD SUSPIE DADDIE SUSP DADD TPWD RPWD Function SUSPIE Suspend Interrupt Enable/Disable bit Suspend interrupt generation is disabled.
Page 127 On-Chip Peripheral Components C541U USB Module Data Register USBDRn, n=0..7 (Address E8 H - EF H ) Bit No. E8 H USBDR0 USBDR1 E9 H EA H USBDR2 EB H USBDR3 USBDR4 EC H USBDR5 ED H EE H USBDR6...
Page 128: Usb Low Speed Interrupts
On-Chip Peripheral Components C541U 6.4.8.6 USB Low Speed Interrupts Each of the USB Low Speed specific interrupt share the vector address of 004B . The general interrupt enable EUEI in IEN1 register has to be enabled, before using these interrupts. The interrupts are cleared by reading USBDCR register.
Page 129: On-Chip Usb Transceiver
C541U 6.4.9 On-Chip USB Transceiver The C541U provides on-chip receiver and transmitter circuitries which allows to connect the C541U directly to the USB bus. The USB driver circuitry is shown in figure 6-35. The USB transceiver is capable of transmitting and receiving serial date at full speed (12 MBits/s) and low speed (1.5 Mbit/ s) data rates.
Page 130 On-Chip Peripheral Components C541U One Bit Time (12 MB/s) Driver Signal Pins One-Way Trip Cable Delay Signal Pins Pass Input Spec Levels Receiver after one Cable Signal Pins Delay MCT03414 Figure 6-36 Full Speed USB Driver Signal Waveforms For a low speed USB connection the rise and fall time of the signals are greater than 75 ns to keep RFI emissions under FCC class B limits, and less than 300 ns to limit timing delays and signaling skews and distortions.
Page 131: Detection Of Connected Devices
On-Chip Peripheral Components C541U 6.4.10 Detection of Connected Devices Full speed and low speed USB devices are differentiated by the position of the pullup resistor on the downstream end of the cable. Full speed devices are terminated with the pull-up on the D+ line and low speed devices are terminated with the pull-up in the D- line (see figure 6-).
Page 132: Detach / Attach Detection
On-Chip Peripheral Components C541U 6.4.11 Detach / Attach Detection The USB device can be used in two different modes concerning its power supply, the bus-powered mode and the self-powered mode. 6.4.11.1 Self-Powered Mode In self-powered mode, the USB device has its own power supply. The USB device has to detect whether it is connected to USB bus or not.
Page 133 On-Chip Peripheral Components C541U Semiconductor Group 6-88 1999-04-01...
Page 134: Interrupt System
C541U Interrupt System The C541U provides seven interrupt sources with two priority levels. Five interrupts can be generated by the on-chip peripherals (timer 0, timer 1, SSC interface, and USB module), and two interrupts may be triggered externally (P3.2/INT0 and P3.3/INT1).
Page 135 Interrupt System C541U Endpoint Interrupts Low Speed Interrupts Endpoint 4 Interrupts SUSP SUSPIE Endpoint 3 Interrupts USBPWD.3 USBPWD.5 Endpoint 2 Interrupts ≥1 DADD Endpoint 1 Interrupts DADDIE USBPWD.2 USBPWD.4 Endpoint 0 Interrupts SETUP packet ACK0 AIE0 OUT packet EPIR0.7 EPIE0.7...
Page 136 Interrupt System C541U Device Interrupts SE0I SE0IE DIRR.7 DIER.7 DAIE DIRR.6 DIER.6 Low Priority DDIE DIRR.5 DIER.5 High Priority ≥1 SBIE DIRR.4 DIER.4 0053 EUDI PUDI SEIE DIRR.3 IEN1.2 DIER.3 IP1.2 STIE DIRR.2 DIER.2 SUIE DIRR.1 DIER.1 SOFI SOFIE DIRR.0 DIER.0...
Page 137: Interrupt Registers
Interrupt System C541U Interrupt Registers 7.1.1 Interrupt Enable Registers Each interrupt vector can be individually enabled or disabled by setting or clearing the corresponding bit in the interrupt enable registers IEN0 or IEN1. Register IEN0 also contains the global disable bit (EA), which can be cleared to disable all interrupts at once. The SSC and USB interrupts sources have further enable bits for individual interrupt control.
Page 138 Interrupt System C541U Special Function Registers IEN1 (Address A9 H ) Reset Value : XXXXX000 B Special Function Registers SCIEN (Address AC H ) Reset Value : XXXXXX00 B Bit No. A9 H – – – – – EUDI EUEI...
Page 139 Interrupt System C541U Special Function Registers DIER (Address C3 H ) Reset Value : 00 H Bit No. C3 H DIER SE0IE DAIE DDIE SBIE SEIE STIE SUIE SOFIE For accessing DIER, SFR EPSEL must be 80 H Function SE0IE USB single ended zero interrupt enable If SE0IE=0, the single ended zero interrupt is disabled.
Page 140 Interrupt System C541U Special Function Register DPWDR (Address C2 H ) Reset Value : 00 H Bit No. MSB E6 H DRVIE TPWD RPWD DPWDR Function DRVIE Device request value interrupt enable Setting bit DRVIE enables the generation of a device interrupt each time the...
Page 141 Interrupt System C541U Special Function Registers EPIEn, n=0-4 (Address C3 H ) Reset Value : 00 H Bit No. C3 H EPIEn AIEn NAIEn RLEIEn – DNRIEn NODIEn EODIEn SODIEn For accessing EPIEn, SFR EPSEL must be 0n H Function...
Page 142 Interrupt System C541U Endpoint n Buffer Control RegisterEPBCn, n=0-4 (Address C1 H ) Reset Value : 00 H Bit No. C1 H EPBCn STALLn GEPIEn SOFDEn INCEn DBMn The shaded bits are not used for interrupt control. Function GEPIEn Global endpoint interrupt enable Bit GEPIEn enables or disables the generation of the global endpoint interrupt forr endpoint n based on the endpoint specific interrupt request bits in register EPIRn.
Page 143: Interrupt Request / Control Flags
Interrupt System C541U 7.1.2 Interrupt Request / Control Flags The external interrupts 0 and 1 (INT0 and INT1) can each be either level-activated or negative transition-activated, depending on bits IT0 and IT1 in register TCON. The flags that actually generate these interrupts are bits IE0 and lE1 in TCON. When an external interrupt is generated, the flag that generated this interrupt is cleared by the hardware when the service routine is vectored too, but only if the interrupt was transition-activated.
Page 144 Interrupt System C541U Special Function Register SCF (Address AB H ) Reset Value : XXXXXX00 B Bit No. AB H – – – – – – WCOL Function – Reserved bits for future use. WCOL SSC write collision interrupt flag WCOL set indicates that an attempt was made to write to the shift register STB while a data transfer was in progress and not fully completed.
Page 145 Interrupt System C541U The USB device interrupt request register contains the device specific interrupt flags of the USB module. These flags describe special events of the USB module. If a request flag is set, it is automatically cleared after a read operation of the DIRR register. The most significant bit in GEPIR register contains an additional device specific interrupt flag, but it needs to be cleared by software.
Page 146 Interrupt System C541U Special Function Register GEPIR (Address D6 ResetValue : 00 H Bit No. MSB D6 H DRVI EPI4 EPI3 EPI2 EPI1 EPI0 GEPIR Function DRVI Device request value interrupt Bit DRVI is set each time the host sends device request that contains one...
Page 147 Interrupt System C541U The register EPIRn (n=0-4) contaíns USB endpoint specific interrupt request flags. This SFR is availble for each endpoint. If a request flag in EPIRn is set, it is automatically cleared after a read operation of the EPIRn register.
Page 148 Interrupt System C541U The global endpoint interrupt request register GEPIRn (n=0-4) contaíns one flag for each endpoint which indicates whether one or more of the seven endpoint specific interrupt requests has become active. If a request flag in GEPIR is set, it is automatically cleared after a read operation of the GEPIR register.
Page 149: Interrupt Prioritiy Registers
Interrupt System C541U 7.1.3 Interrupt Prioritiy Registers Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in the SFRs IP0 or IP1 (interrupt priority: 0 = low priority, 1 = high priority).
Page 150: Interrupt Priority Level Structure
Interrupt System C541U Interrupt Priority Level Structure A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low- priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced.
Page 151: How Interrupts Are Handled
Interrupt System C541U How Interrupts are Handled The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are polled during the following machine cycle. If one of the flags was in a set condition at S5P2 of the preceeding...
Page 152 SFR PCON1 is set. If these two conditions are met and when the oscillator watchdog unit start- up phase after a wake-up condition (INT0=0) is finished, the C541U starts with an interrupt at address 007B H . All other interrupts are now disabled until the RETI instruction of the power-down interrupt routine has been executed.
Page 153: External Interrupts
Interrupt System C541U External Interrupts The external interrupts 0 and 1 can be programmed to be level-activated or transition activated by setting or clearing bit IT0 or IT1 in register TCON. If ITx = 0 (x = 0 or 1), external interrupt x is triggered by a detected low level at the INTx pin.
Page 154 Interrupt System C541U The edge-triggered interrupt mode selection for the external interrupts is selected by bits in SFR ITCON (External Interrupt Trigger Condition Register). The edge-trigger mode selection is defined in a way (default value of ITCON after reset), that their function is upward compatible to the basic external interrupt functionality of the C501.
Page 155: Interrupt Response Time
Interrupt System C541U Interrupt Response Time If an external interrupt is recognized, its corresponding request flag is set at S5P2 in every machine cycle. The value is not polled by the circuitry until the next machine cycle. If the request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be next instruction to be executed.
Page 156: Fail Safe Mechanisms
The watchdog timer in the C541U is a 15-bit timer, which is incremented by a count rate of /192. The system clock of the C541U is divided by two prescalers, a divide-by-two and a divide-by-16 prescaler which are selected by bit WDTPSEL (WDTREL.7).
Page 157: Input Clock Selection
C541U 8.1.1 Input Clock Selection The input clock rate of the watchdog timer is derived from the system clock of the C541U. There is a prescaler available, which is software selectable and defines the input clock rate. This prescaler is controlled by bit WDTPSEL in the SFR WDTREL. Tabel 8-1 shows resulting timeout periods at = 12 MHz.
Page 158: Watchdog Timer Control / Status Flags
Fail Safe Mechanisms C541U 8.1.2 Watchdog Timer Control / Status Flags The watchdog timer is controlled by control and status flags which are located in SFR WDCON. Special Function Register WDCON (Address C0 H ) Reset Value : XXXX 0000 B Bit No.
Page 159: Starting The Watchdog Timer
Fail Safe Mechanisms C541U 8.1.3 Starting the Watchdog Timer The watchdog timer can be started by software (bit SWDT in SFR WDCON), but it cannot be stopped during active mode of the device. If the software fails to clear the watchdog timer an internal reset will be initiated.
Page 160: Oscillator Watchdog Unit
Fail Safe Mechanisms C541U Oscillator Watchdog Unit The oscillator watchdog unit serves for three functions: – Monitoring of the on-chip oscillator’s function The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset;...
Page 161: Functionality Of The Oscillator Watchdog Unit
At the same time the watchdog activates the internal reset in order to bring the C541U in its defined reset state. The reset is performed because a clock is available from the RC oscillator. This internal watchdog reset has the same effects as an externally applied reset signal with the following exceptions: The watchdog timer status flag WDTS is not reset (the watchdog timer however is stopped) and bit OWDS is set.
Page 162: Fast Internal Reset After Power-On
8.2.2 Fast Internal Reset after Power-On The C541U can use the oscillator watchdog unit for a fast internal reset procedure after power-on. Normally the members of the 8051 family (e. g. SAB 80C52) enter their default reset state not before the on-chip oscillator starts.
Page 163 Fail Safe Mechanisms C541U Semiconductor Group 1997-10-01...
Page 164: Power Saving Modes
Power Saving Modes C541U Power Saving Modes The C541U provides two power saving modes : – Idle mode – Power down mode. The functions of the power saving modes are controlled by bits which are located in the special function registers PCON und PCON1. PCON is located at address 87 H . PCON1 is located in the mapped SFR area and is accessed with RMAP=1.
Page 165 Power Saving Modes C541U Special Function Register PCON (Address 87 H) Reset Value : X00X0000 B Special Function Register PCON1 (Mapped Address 88 H) Reset Value : 0XX0XXXX B Bit No. 87 H – IDLS – IDLE PCON 88 H EWPD –...
Page 166: Idle Mode
C541U Idle Mode In the idle mode the main oscillator of the C541U continues to run, but the CPU is gated off from the clock signal. However, the interrupt system, the SSC, the USB module, and the timers with the exception of the watchdog timer are further provided with the clock.
Page 167: Entering Idle Mode
Power Saving Modes C541U 9.1.1 Entering Idle Mode The idle mode is entered by two consecutive instructions. The first instruction sets the flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5), the following instruction sets the start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0).
Page 168: Power Down Mode
Power Saving Modes C541U Power Down Mode In the power down mode, the RC osciillator and the on-chip oscillator which operates with the XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR’s are maintained.
Page 169: Entering Power Down Mode
Power Saving Modes C541U 9.2.1 Entering Power Down Mode The power down mode is entered by two consecutive instructions. The first instruction has to set the flag bit PDE (PCON.1) and must not set bit PDS (PCON.6), the following instruction has to set the start bit PDS (PCON.6) and must not set bit PDE (PCON.1).
Page 170: Exit From Power Down Mode
Power Saving Modes C541U 9.2.2 Exit from Power Down Mode If the power down mode is exit via a hardware reset, the microcontroller with its SFRs is put into the hardware reset state and the content of RAM and XRAM are not changed. The reset signal that terminates the power down mode also restarts the RC oscillator and the on-chip oscillatror.
Page 171: Exit Via Pin P3.2/Int0
The peripheral units timer 0/1, SSC, and WDT are frozen until end of phase 4. All interrupts of the C541U are disabled from phase 2) until the end of phase 4). Other Interrupts can be first handled after the RETI instruction of the wake-up interrupt routine.
Page 172: Otp Memory Operation
PSEL are used. Further, the inputs PMSEL1,0 are required to select the access types (e.g. program/verify data, write lock bits, ..) in the programming mode. In programming mode V and a clock signal at the XTAL pins must be applied to the C541U. The 11.5V external programming voltage is input through the EA/V pin.
Page 173: Pin Configuration
OTP Memory Operation C541U 10.2 Pin Configuration Figure 10-2 shows the detailed P-LCC-44 pin configuration of the C541U in programming mode. 44 43 42 41 40 N.C. RESET PMSEL0 EA/V C541U N.C. N.C. PMSEL1 PROG Programming PSEL PSEN Mode PALE...
Page 174: Pin Definitions
OTP Memory Operation C541U 10.3 Pin Definitions The following table 10-1 contains the functional description of all C541U pins which are required for OTP memory programming Table 10-1 Pin Definitions and Functions in Programming Mode Symbol Pin Num- I/O*) Function...
Page 175 D0 - 7 43 - 36 Data lines 0-7 During programming mode, data bytes are read or written from or to the C541U via the bidirectional D0-7 lines which are located at port 0. 9, 22 – Circuit ground potential must be applied to these pins in programming mode.
Page 176: Programming Mode Selection
OTP Memory Operation C541U 10.4 Programming Mode Selection The selection for the OTP programming mode can be separated into two different parts : – Basic programming mode selection – Access mode selection With the basic programming mode selection the device is put into the mode in which it is possible to access the OTP memory through the programming interface logic.
Page 177: Otp Memory Access Mode Selection
! 10.4.2 OTP Memory Access Mode Selection When the C541U has been put into the programming mode using the basic programming mode selection, several access modes of the OTP memory programming interface are available. The conditions for the different control signals of these access modes are listed in table 10-2.
Page 178: Program / Read Otp Memory Bytes
MCT03419 Figure 10-4 C541U Programming / VerifyOTP Memory Access Waveform If the address lines A8-A12 must be updated, PALE must be activated for the latching of the new A8- A12 value. Control, address, and data information must only be switched when the PROG and PRD signals are at high level.
Page 179 OTP Memory Operation C541U Figure 10-5 shows a waveform example of the program/read mode access for several OTP memory bytes. In this example OTP memory locations 3FD H to 400 H are programmed. Thereafter, OTP memory locations 400 H and 3FD H are read.
Page 180: Lock Bits Programming / Read
Note : A 1 means that the lock bit is unprogrammed. 0 means that lock bit is programmed. For a OTP verify operation at protection level 1, the C541U must be put into the OTP verification mode 2.
Page 181 OTP Memory Operation C541U PMSEL1,0 PALE Port 0 (D1, D0) PROG MCT03421 The example shows the programming and reading of a protection level 1. Figure 10-6 Write/Read Lock Bit Waveform Semiconductor Group 10-10 1997-10-01...
Page 182: Access Of Version Bytes
Access of Version Bytes The C541U provides three version bytes at address locations FC H , FD H , and FE H . The information stored in the version bytes, is defined by the mask of each microcontroller step, Therefore, the version bytes can be read but not written.
Page 183: Otp Verify With Protection Level
OTP Verify with Protection Level 1 If the C541U OTP program memory is protected in protection level 1), an OTP verification as shown in figure 10-8 is used to verify the content of the OTP. The detailed timing characteristics of this OTP verification mode is shown in the AC specifications (chapter 11).
Page 184 Figure 10-9 shows an application example of a external circuitry which allows to verify a protected OTP inside the. With RESET going inactive, the C541U starts the OTP verify sequence. Its ALE is clocking an 14-bit address counter. This counter generates the addresses for an external EPROM which is programmed with the content of the internal (protected) OTP.
Page 185 OTP Memory Operation C541U Semiconductor Group 10-14 1997-10-01...
Page 186: Index
Index C541U Index CLREPn......6-69 CPHA..... . 3-6, 6-30 Note : Bold page numbers refer to the main definition CPOL .
Page 187 Index C540U / C541U DNRIEn ....6-70, 7-8 EPI4-0 ....3-7, 6-58, 7-15 DNRn .
Page 188 Index C541U F1 ......2-3, 3-7 Registers ....7-4 to 7-16 Fail save mechanisms .
Page 189 Index C540U / C541U NOD2 ......3-10 Parallel I/O ....6-1 to 6-14 NOD3 .
Page 190 Index C540U / C541U RLE2 ......3-10 SODIE3 ......3-10 RLE3 .
Page 191 Index C540U / C541U SYSCON ... . . 3-3, 3-4, 3-7, 4-4 Memory buffer address generation . 6-50 Memory buffer modes ..6-36 to 6-48 Double buffer mode ..6-42 to 6-48 T0 .
Page 192 Index C541U Semiconductor Group 12-7...

Siemens C541U User Manual

Introduction

Fundamental Structure

Memory Organization

External Bus Interface

PSEN, Program Store Enable

Reset and System Clock Operation

On-Chip Peripheral Components

Interrupt System

Fail Safe Mechanisms

Power Saving Modes

OTP Memory Operation

Index

Quick Links

Related Manuals for Siemens C541U

Summary of Contents for Siemens C541U

Table of Contents