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Memory Operating Mode
Dell Fault Resilient Mode
Optimizer Mode
This mode supports Single Device Data Correction (SDDC) only for memory modules that use x4 device width. It does not impose any
specific slot population requirements.
•
Dual processor: Populate the slots in round robin sequence starting with processor 1.
NOTE:
Processor 1 and processor 2 population should match.
Table 55. Memory population rules
Processor
Configuration
Single processor
Optimizer (Independent
channel) population order
Mirror population order
Single rank sparing
population order
Multi rank sparing
population order
Fault resilient population
order
Dual processor (Start
Optimized (Independent
with processor1.
channel) population order
processor1 and
processor 2 population
should match)
Description
NOTE:
To use memory sparing, this feature must be
enabled in the BIOS menu of System Setup.
NOTE:
Memory sparing does not offer protection against
a multi-bit uncorrectable error.
The Dell Fault Resilient Mode if enabled, the BIOS creates an
area of memory that is fault resilient. This mode can be used by an
OS that supports the feature to load critical applications or enables
the OS kernel to maximize system availability.
Memory population
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
12
{1, 2, 3, 4, 5, 6} {7, 8, 9, 10,
11, 12}
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
12
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
12
{1, 2, 3, 4, 5, 6} {7, 8, 9, 10,
11, 12}
A{1}, B{1},
A{2}, B{2},
A{3}, B{3},
A{4}, B{4},
A{5}, B{5},
A{6}, B{6}
Installing and removing system components
Memory population information
•
DIMMs must be populated in the order
specified.
•
Odd number of DIMM population is allowed
NOTE:
Odd number of DIMMs will
result in unbalanced memory
configurations, which in turn will result
in performance loss. It is recommended
to populate all memory channels
identically with identical DIMMs for
best performance.
•
Optimizer population order is not traditional for
4 and 8 DIMM installations of single processor.
•
For 4 DIMMs: A1, A2, A4, A5
•
For 8 DIMMs: A1, A2, A4, A5, A7, A8, A10,
A11
Mirroring is supported with 6 or 12 DIMMs per
processor.
•
DIMMs must be populated in the order
specified.
•
Requires two ranks or more per channel.
•
DIMMs must be populated in the order
specified.
•
Requires three ranks or more per channel.
Supported with 6 or 12 DIMMs per processor.
Odd number of DIMM population per processor is
allowed.
NOTE:
Odd number of DIMMs will result in
unbalanced memory configurations, which
in turn will result in performance loss. It is
recommended to populate all memory
99
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