Pci Configuration Space Functions - Realtek RTL8169 Manual

3Eh MNGNT R
3Fh MXLAT R
40h–
5Fh
60h VPDID R
61h NextPtr R
62h Flag VPD R/W VPDADDR
Address
63h R/W
64h VPD Data R/W
65h R/W
66h R/W
67h R/W
68h-
DBh
DCh PMID R
DDh NextPtr R
DEh PMC R
DFh R
E0h PMCSR R
W
E1h R
W
E2h-
FFh
The above table is based on both VPD and Power Management are enabled.

8.5 PCI Configuration Space Functions

The PCI configuration space is intended for configuration, initialization, and catastrophic error handling functions. The
functions of the RTL8169's configuration space are described below.
VID: Vendor ID. This field will be set to a value corresponding to PCI Vendor ID in the external EEPROM. If there is no
EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI Vendor ID.
DID: Device ID. This field will be set to a value corresponding to PCI Device ID in the external EEPROM. If there is no
EEPROM, this field will default to a value of 8129h.
Command: The command register is a 16-bit register used to provide coarse control over a device's ability to generate and
respond to PCI cycles.
Bit Symbol
15:10 -
9 FBTBEN
8 SERREN
7 ADSTEP
cont...
2002/03/27
0 0
0 0
0 0
0 0
VPDADDR
7 6
Flag VPDADDR
14
Data7 Data6
Data15 Data14
Data23 Data22
Data31 Data30
0 0
0 1
Aux_I_b1 Aux_I_b0
PME_D3 PME_D3
cold
0 0
- -
PME_Status -
PME_Status -
Reserved
Fast Back-To-Back Enable: Config3<FBtBEn>=0:Read as 0. Write operation has no effect. The
RTL8169 will not generate Fast Back-to-back cycles. When Config3<FbtBEn>=1, This read/write bit
controls whether or not a master can do fast back-to-back transactions to different devices.
Initialization software will set the bit if all targets are fast back-to-back capable. A value of 1 means
the master is allowed to generate fast back-to-back transaction to different agents. A value of 0 means
fast back-to-back transactions are only allowed to the same agent. This bit's state after RST# is 0.
System Error Enable: When set to 1, the RTL8169 asserts the SERRB pin when it detects a parity
error on the address phase (AD<31:0> and CBEB<3:0> ).
Address/Data Stepping: Read as 0, and write operations have no effect. The RTL8169 never
performs address/data stepping.
1 0
1 0
RESERVED
0 0
0 0
VPDADD VPDADD
R5 R4
VPDADD VPDADD
R13 R12
Data5 Data4
Data13 Data12
Data21 Data20
Data29 Data28
RESERVED
0 0
1 0
DSI Reserved PMECLK
PME_D2 PME_D1 PME_D0
hot
0 0
- -
- -
- -
RESERVED
Description
42
0 0
0 0
0 0
0 0
VPDADD VPDADD VPDADD
R3 R2
VPDADD VPDADD VPDADD
R11 R10
Data3 Data2
Data11 Data10
Data19 Data18
Data27 Data26
0 0
0 0
D2
0 0
- -
- -
- -
RTL8169
0 0
0 0
1 1
0 0
VPDADD
R1 R0
VPDADD
R9 R8
Data1 Data0
Data9 Data8
Data17 Data16
Data25 Data24
0 1
0 0
Version
D1 Aux_I_b2
Power State
Power State
- PME_En
- PME_En
Rev.1.21