Functional Description; Transmit & Receive Operations; Transmit - Realtek RTL8169 Manual

RTL8169

9. Functional Description

9.1 Transmit & Receive Operations
The RTL8169 supports a new descriptor-based buffer management that will significantly reduce host CPU utilization and is
more suitable for a server application. The new buffer management algorithm provides capabilities of Microsoft Large-Send
offload, IP checksum offload, TCP checksum offload, UDP checksum offload, and IEEE802.1P, 802.1Q VLAN tagging. The
RTL8169 supports up to 1024 consecutive descriptors in memory for transmit and receive separately, which means there might
be 3 descriptor rings, one is a high priority transmit descriptor ring, another is a normal priority transmit descriptor ring, and the
other is a receive descriptor ring, each descriptor ring may consist of up to 1024 4-double-word consecutive descriptors. Each
descriptor consists of 4 consecutive double words. The start address of each descriptor group should be 256-byte alignment.
Software must pre-allocate enough buffers and configure all descriptor rings before transmitting and/or receiving packets.
Descriptors can be chained to form a packet in both Tx and Rx. Please refer to the Realtek RTL8169 programming guide for
detailed information. Any Tx buffers pointed to by one of Tx descriptors should be at least 4 bytes.
Padding: The RTL8169 will automatically pad any packets less than 64 bytes (including 4 bytes CRC) to 64-byte long (including
4-byte CRC) before transmitting that packet onto network medium.
If a packet consists of 2 or more descriptors, then the descriptors in command mode should have the same configuration, except
EOR, FS, LS bits.

9.1.1 Transmit

This portion implements the transmit portion of 802.3 Media Access Control. The Tx MAC retrieves packet data from the Tx
Buffer Manager and sends it out through the transmit physical layer interface. Additionally, the Tx MAC provides MIB control
information for transmit packets. The Tx MAC supports 4-bit MII, 8-bit GMII, and 10-bit TBI interfaces to physical layer
devices.
The Tx MAC has the capability to insert a 4-byte VLAN tag in the transmit packet. If Tx VLAN Tag insertion is enabled, the
MAC will insert the 4 bytes, as specified in the VTAG register, following the source and destination addresses of the packet. The
VLAN tag insertion can be enabled on a global or per-packet basis.
When operating in 1G mode, the RTL8169 operates in full duplex mode only.
The Tx MAC supports task offloading of IP, TCP, and UDP checksum generation. It can generate the checksums and insert them
into the packet. The checksum generation can be enabled on a global or per-packet basis.
The following information describes what the Tx descriptor may look like, depending on different states in each Tx descriptor.
The minimum Tx buffer should be at least 4 bytes.
2002/03/27 Rev.1.21
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