Transmit Configuration - Realtek RTL8169 Manual

6.8 Transmit Configuration

(Offset 0040h-0043h, R/W)
Bit R/W
31 -
30:26 R
25:24 R/W
23 R
22:20
19 R/W
18:17 R/W
16 R/W
15:11 -
cont...
2002/03/27
Symbol
-
Reserved
HWVERID0
Hardware Version ID0:
RTL8139
RTL8139A
RTL8139A-G
RTL8139B
RTL8130
RTL8139C
RTL8139C+
RTL8100
RTL8169
Reserved
IFG1, 0 InterFrameGap Time: This field allows adjustment of the interframe
gap time to be longer than the standards of 9.6 µs for 10Mbps, 960 ns
for 100Mbps, and 96 ns for 1000Mbps. The time can be programmed
from 9.6 µs to 14.4 µs (10Mbps), 960ns to 1440ns (100Mbps), and 96ns
to 144ns (1000Mbps).
The setting of the inter frame gap is:
IFG[2:0]
0
1
1
0
0
-Other values are reserved.
HWVERID1 Hardware Version ID1: Please see HWVERID0.
- Reserved
IFG2 InterFrameGap2
LBK1, LBK0 Loopback test: There will be no packets on the (G)MII or TBI interface
in Digital loopback mode, provided the external phyceiver is also set in
loopback mode. The digital loopback function is independent of the
current link status.
For analog loopback tests, software must force the external phyceiver
into loopback mode while the RTL8169 operates normally.
00 : Normal operation
01 : Digital loopback mode
10 : Reserved
11 : Reserved
CRC Append CRC: Setting this bit to 1 means that there is no CRC
appended at the end of a packet. Setting to 0 means that there is a CRC
appended at the end of a packet.
-
Reserved
Description
Bit30 Bit29
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 0
IFG@1000MHz
(ns)
1 1 96
0 1 96 + 8
1 1 96 + 16
0 1 96 + 24
1 0 96 + 48
20
Bit28 Bit27 Bit26
0 0 0
1 0 0
1 0 0
1 1 0
1 1 1
1 0 1
1 0 1
1 1 0
0 0 0
All other combination
IFG@100MHz IFG@10MHz
(ns)
960
960 + 8 * 10 9.6 + 8 * 0.1
960 + 16 * 10 9.6 + 16 * 0.1
960 + 24 * 10 9.6 + 24 * 0.1
960 + 48 * 10 9.6 + 48 * 0.1
RTL8169
Bit23
0
0
1
0
0
0
1
1
0
(µs)
9.6
Rev.1.21