Configuration Access; Packet Buffering; Transmit Buffer Manager; Receive Buffer Manager - Realtek RTL8169 Manual

RTL8169

8.2.5 Configuration Access

Configuration register accesses are similar to target reads and writes in that they are single data word transfers and are initiated
by the system. For the system to initiate a Configuration access, it must also generate IDSEL as well as the correct Command
(1010b or 1011b) during the Address phase. The RTL8169 will respond as it does during Target operations. Configuration reads
must be 32-bits wide, but writes may access individual bytes.

8.3 Packet Buffering

The RTL8169 incorporates two independent FIFOs for transferring data to/from the system interface and from/to the network.
The FIFOs, providing temporary storage of data freeing the host system from the real-time demands of the network.
The way in which the FIFOs are emptied and filled is controlled by the FIFO threshold values in the Transmit Configuration and
Receive Configuration registers. These values determine how full or empty the FIFOs must be before the device requests the
bus. Additionally, there is a threshold value that determines how full the transmit FIFO must be before beginning transmission.
Once the RTL8169 requests the bus, it will attempt to empty or fill the FIFOs as allowed by the respective MXDMA settings in
the Transmit Configuration and Receive Configuration registers.

8.3.1 Transmit Buffer Manager

The buffer management scheme used on the RTL8169 allows quick, simple and efficient use of the frame buffer memory. The
buffer management scheme uses separate buffers and descriptors for packet information. This allows effective transfers of data
to the transmit buffer manager by simply transferring the descriptor information to the transmit queue.
The Tx Buffer Manager DMAs packet data from system memory and places it in the 8KB transmit FIFO, and pulls data from the
FIFO to send to the Tx MAC. Multiple packets may be present in the FIFO, allowing packets to be transmitted with minimum
interframe gap. The way in which the FIFO is emptied and filled is controlled by the ETTH (Early Transmit Threshold) and
RXFTH (Rx FIFO Threshold) values. Additionally, once the RTL8169 requests the bus, it will attempt to fill the FIFO as
allowed by the MXDMA setting.
The Tx Buffer Manager process also supports priority queuing of transmit packets. It handles this by drawing from two separate
descriptor lists to fill the internal FIFO. If packets are available in the high priority queues, they will be loaded into the FIFO
before those of low priority.

8.3.2 Receive Buffer Manager

The Rx Buffer Manager uses the same buffer management scheme as used for transmits. The Rx Buffer Manager retrieves
packet data from the Rx MAC and places it in the 32KB receive data FIFO, and pulls data from the FIFO for DMA to system
memory. Similar to the transmit FIFO, the receive FIFO is controlled by the FIFO threshold value in RXFTH. This value
determines the number of long words written into the FIFO from the MAC unit before a DMA request for system memory
occurs. Once the RTL8169 gets the bus, it will continue to transfer the long words from the FIFO until the data in the FIFO is less
than one long word, or has reached the end of the packet, or the max DMA burst size is reached , as set in MXDMA.

8.3.3 Packet Recognition

The Rx packet filter and recognition logic allows software to control which packets are accepted, based on destination address
and packet type. Address recognition logic includes support for broadcast, multicast hash, and unicast addresses. The packet
recognition logic includes support for WOL, Pause, and programmable pattern recognition.
2002/03/27 Rev.1.21
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