Tbi Timing - Realtek RTL8169 Manual

Gigabit ethernet media access controller with power management
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11.3.6 TBI Timing

tRC
GTxCLK
Tx[9:0]
RxCLK0
Rx[9:0]
RxCLK1
Symbol
tTxCC
Tx Clock Cycle
fGTxCLK
GTxCLK frequency
tRC
Clock Rise Time of GTxCLK,
RxCLK0, RxCLK1
tFC
Clock Fall Time of GTxCLK,
RxCLK0, RxCLK1
tDUTY
Clock Duty Cycle of GTxCLK,
RxCLK0, RxCLK1
Data Setup to ↑ of GTxCLK
tTxSU
Data Hold from ↑ of GTxCLK
tTxHT
tRD
Data Rise Time of Tx[9:0],
Rx[9:0]
rFD
Data Fall Time of Tx[9:0],
Rx[9:0]
fRxCLKx
RxCLK0, RxCLK1 frequency
tDRIFT
RxCLK0/1 Drift Rate
Data Setup to ↑ of RxCLK0/1
tRxSU
Data Hold after ↑ of RxCLK0/1
tRxHT
tA-B
TBI RxCLK Skew
2002/03/27
tTxCC
tRD
tFD
TBI Tx Timing
tA-B
tRxSU
tRxHT
TBI Rx Timing
Description
125 – 100ppm
TBI Timing Parameters
tFC
tTxSU
tTxHT
Valid Data
tRxSU
tRxHT
Min
Typical
8
125
0.7
0.7
40
2.0
1.0
0.7
0.7
62.5
0.2
2.5
1.5
7.5
90
RTL8169
2.0V
1.4V
0.8V
2.0V
0.8V
1.4V
2.0V
0.8V
1.4V
Max
Units
ns
125 + 100ppm
MHz
2.4
ns
2.4
ns
60
%
ns
ns
ns
ns
MHz
us/MHz
ns
ns
8.5
ns
Rev.1.21

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