Clock And Nc Pins; Power Pins - Realtek RTL8169 Manual

CRS I
MDC O
MDIO I/O
TBILBK O
RSTPHYB O

5.6 Clock and NC Pins

Symbol Type
Clock125 I
NC -

5.7 Power Pins

Symbol Type
VDD33 P
VDD18 P
GND P
2002/03/27
148
169
170
133
132
Pin No
168
2, 4, 6, 45, 47, 49, 51,
103, 106, 108, 153,
155,
Pin No
8, 18, 30, 41, 55, 65,
77, 89, 113, 131, 144,
167, 179, 189, 200
27, 120, 68, 166
13, 23, 36, 48, 60, 71,
82, 98, 117, 134, 150,
171, 184, 195, 206, 33,
94, 72, 149
Carrier Sense: In GMII or MII mode, this pin is asserted high by the
GMII/MII PHY device whenever the transmit or receive medium is not
idle, and is deasserted when both transmit and receive media are idle.
The CRS remains asserted throughout the duration of a collision
condition. The CRS transitions asynchronously with respect to RxCLK,
GTxCLK, or TxCLK.
In TBI mode, this pin's status is ignored by the RTL8169.
Management Data Clock: In GMII or MII mode, it is a synchronous
clock to the MDIO management data input/output serial interface (about
3.125MHz) which may be asynchronous to transmit and receive clocks.
In TBI mode, this pin is a reserved pin.
Management Data Input/Output: Bi-directional signal used to
transfer or receive control and status information from the PHY device.
MDIO is driven and sampled synchronously with respect to MDC.
In TBI mode, this pin is a reserved pin.
TBI LoopBack: The RTL8169 asserts this pin high when the TBI is in
loopback mode.
PHY Reset pin: An active low signal used by the RTL8169 to force
hardware reset to external PHYceiver at initial power-on.
125MHz clock input: The 125MHz reference clock for the RTL8169
comes from either external PHYceiver or 125MHz OSC.
Reserved
+3.3V
+1.8V
Ground
12
Description
Description
RTL8169
Rev.1.21