Pci Configuration Space Registers; Pci Bus Interface; Byte Ordering; Interrupt Control - Realtek RTL8169 Manual

8. PCI Configuration Space Registers

8.1 PCI Bus Interface

The RTL8169 implements the PCI bus interface as defined in the PCI Local Bus Specifications Rev. 2.2. When internal registers
are being accessed, the RTL8169 acts as a PCI target (slave mode). When accessing host memory for descriptor or packet data
transfer, the RTL8169 acts as a PCI bus master.
All of the required pins and functions are implemented in the RTL8169 as well as the optional pin, INTAB for support of interrupt
requests is implemented as well. The bus interface also supports 64-bit and 66Mhz operation in addition to the more common 32-bit
and 33-Mhz capabilities. For more information, refer to the PCI Local Bus Specifications Rev. 2.2, December 18, 1998.

8.1.1 Byte Ordering

The RTL8169 can be configured to order the bytes of data on the PCI AD bus to conform to little-endian or big-endian ordering
through the use of the ENDIAN bit of the C+ Command Register. When the RTL8169 is configured in big-endian mode, all the
data in the data phase of either memory or I/O transaction to or from RTL8169 is in big-endian mode. All data in the data phase
of any PCI configuration transaction to the RTL8169 should be in little-endian mode, regardless if the RTL8169 is set to
big-endian or little-endian mode.
When configured for little-endian mode (ENDIAN bit=0), the byte orientation for receive and transmit data and descriptors in
system memory is as follows:
31
When configured for big-endian mode (ENDIAN bit=1), the byte orientation for receive and transmit data and descriptors in
system memory is as follows:
31

8.1.2 Interrupt Control

Interrupts are performed by asynchronously asserting the INTAB pin. This pin is an open drain output. The source of the
interrupt can be determined by reading the Interrupt Status Register (ISR). One or more bits in the ISR will be set, denoting all
currently pending interrupts. Writing 1 to any bit in the ISR register clears that bit. Masking of specific interrupts can be
accomplished by using the Interrupt Mask Register (IMR). Assertion of INTAB can be prevented by clearing the Interrupt
Enable bit in the Interrupt Mask Register. This allows the system to defer interrupt processing as needed.

8.1.3 Latency Timer

The PCI Latency Timer described in LTR defines the maximum number of bus clocks that the device will hold the bus. Once the
device gains control of the bus and issues FRAMEB, the Latency Timer will begin counting down. The LTR register specifies,
in units of PCI bus clocks, the value of the latency timer of the RTL8169. When the RTL8169 asserts FRAMEB, it enables its
latency timer to count. If the RTL8169 deasserts FRAMEB prior to count expiration, the content of the latency timer is ignored.
Otherwise, after the count expires, the RTL8169 initiates transaction termination as soon as its GNTB is deasserted. Software is
able to read or write to LTR, and the default value is 00H.
2002/03/27
24 23
Byte 3 Byte 2
C/BE[3] C/BE[2]
(MSB)
Little-Endian Byte Ordering
24 23
Byte 0 Byte 1
C/BE[3] C/BE[2]
(LSB)
Big-Endian Byte Ordering
16 15 8
Byte 1
C/BE[1]
16 15 8
Byte 2
C/BE[1]
36
7 0
Byte 0
C/BE[0]
(LSB)
7 0
Byte 3
C/BE[0]
(MSB)
RTL8169
Rev.1.21